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Channel Register Bit Descriptions

THS7347

SLOS531 – MAY 2007

Each bit of the subaddress (channel selection) control register as described in the previous section allows the

user to individually control the THS7347 functionality. This process allows the user to control the functionality of

each channel independently with regard to the other channels. The bit description for Channel 1 through

Channel 3 is shown in Table 3, while the H/V sync channels and the analog channel states are described in

Table 4.

Table 3. THS7347 Channel Register (Channel 1 through Channel 3) Bit Decoder Table.

Use with Register Bit Codes (0000 0001), (0000 0010), and (0000 0011)

BIT

FUNCTION

BIT VALUE(S)

RESULT

0

500-kHz filter on the STC circuit

(MSB)

Sync-Tip Clamp Filter

7

1

5-MHz filter on the STC circuit

0 0 0 0

MUX Input A

0 0 0 1

MUX Input A

0 0 1 0

MUX Input A

0 0 1 1

MUX Input A

0 1 0 0

MUX Input A

0 1 0 1

MUX Input B

0 1 1 0

MUX Input B

0 1 1 1

MUX Input B

6, 5, 4, 3

MUX Selection

1 0 0 0

MUX Input B

1 0 0 1

MUX Input B

1 0 1 0

Reserved; do not care

1 0 1 1

Reserved; do not care

1 1 0 0

Reserved; do not care

1 1 0 1

Reserved; do not care

1 1 1 0

Reserved; do not care

1 1 1 1

Reserved; do not care

0 0 0

Disables both monitor and buffer paths of the respective

channel/register

0 0 1

Channel Mute

0 1 0

Input Mode = dc

Input Mode

2, 1, 0

0 1 1

Input Mode = dc + Shift

+

(LSB)

Operation

1 0 0

Input Mode = ac-bias

1 0 1

Input Mode = ac-STC with low bias

1 1 0

Input Mode = ac-STC with mid bias

1 1 1

Input Mode = ac-STC with high bias

Bit 7 (MSB): Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected.

Bits 6, 5, 4, 3: Selects the Input MUX channel.

Bits 2, 1, and 0 (LSB): Configures the channel mode and operation. See Table 4, Bits 6 and 5, for more

information with respect to the enable/disable state.

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