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Start

Condition

Stop

Condition

SDA

SCL

S

P

THS7347

SLOS531 – MAY 2007

APPLICATIONS INFORMATION (continued)

developed by Philips Semiconductor (see the I2C Bus Specification, Version 2.1, January 2000). The THS7347

was designed in compliance with version 2.1 specifications. The bus consists of a data line (SDA) and a clock

line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the

usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating

the SCL signal and device addresses. The master also generates specific conditions that indicate the START

and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master

device. The THS7347 works as a slave and supports the standard mode transfer (100 kbps) and fast mode

with the high-speed mode (3.4 Mbps) but it is not specified at this time.

The basic access cycle consists of the following:

• A start condition

• A slave address cycle

• Any number of data cycles

• A stop condition

• The master initiates data transfer by generating a start condition. The start condition exists when a

devices should recognize a start condition.

• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 6). All devices

recognize the address sent by the master and compare it to the respective internal fixed addresses. Only the

slave device with a matching address generates an acknowledge (see Figure 7) by pulling the SDA line low

during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a

communication link with a slave has been established.

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