PCF8535 datasheet(31/52 Pages) PHILIPS

31 / 52 page

1999 Aug 24

Philips Semiconductors

Objective speciﬁcation

× 133 pixel matrix driver

PCF8535

7.17.2

I2C-BUS PROTOCOL

The PCF8535 is a slave receiver/transmitter. If data is to

be read from the device the SDAOUT pad must be

connected, otherwise SDAOUT is unused.

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed. Four slave

addresses, 0111100, 0111101, 0111110 and 0111111 are

reserved for the PCF8535. The Least Significant Bits

(LSBs) of the slave address is set by connecting

SA1 and SA0 to either logic 0 (VSS) or logic 1 (VDD).

A sequence is initiated with a START condition (S) from

the I2C-bus master which is followed by the slave address.

All slaves with the corresponding address acknowledge in

parallel, all the others will ignore the I2C-bus transfer.

After the acknowledgement cycle of a write, a control byte

follows which defines the destination for the forthcoming

data byte and the mode for subsequent bytes. For a read,

the PCF8535 will immediately start to output the requested

data until a NOT acknowledge is transmitted by the

master. The sequence should be terminated by a STOP in

the event that no further access is required for the time

being, or by a RE-START, should further access be

required.

For ease of operation a continuation bit, Co, has been

included. This bit allows the user to set-up the chip

configuration and transmit RAM data in one access. A data

selection bit, D/C, defines the destination for data. These

bits are contained in the control byte. DB5 to DB0 should

be set to logic 0. These bits are reserved for future

expansion.

Table 19 Co and D/C deﬁnitions

An example of a write access is given in Fig.19. Here, multiple instruction data is sent, followed by multiple display bytes.

An example of a read access is given in Fig.20.

BIT

0/1

R/W

ACTION

n.a.

last control byte to be sent: only a stream of data bytes are allowed to follow; this stream may

only be terminated by a STOP or RE-START condition

another control byte will follow the data byte unless a STOP or RE-START condition is received

D/C

data byte will be decoded and used to set up the device

data byte will return the contents of the currently selected status register

data byte will be stored in the display RAM

no provision for RAM read back is provided

Fig.19 Master transmits to slave receiver; write mode.

handbook, full pagewidth

MGS682

S 01111

acknowledgement

from PCF8535

acknowledgement

from PCF8535

acknowledgement

from PCF8535

acknowledgement

from PCF8535

acknowledgement

from PCF8535

control byte

data byte

≥ 0 bytes

1 byte

slave address

MSB . . . . . . . . . . . LSB

≥ 0 bytes

update

data pointer

R/W

A P

D/C

control byte

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