PCF8535 datasheet(5/52 Pages) PHILIPS

5 / 52 page

1999 Aug 24

Philips Semiconductors

Objective speciﬁcation

× 133 pixel matrix driver

PCF8535

5.1

Block diagram functions

5.1.1

OSCILLATOR

The on-chip oscillator provides the display clock for the

system; it requires no external components. Alternatively,

an external display clock may be provided via the OSC

input. The OSC input must be connected to VDD1 or VSS1

when not in use. During power-down additional current

saving can be made if the external clock is disabled.

5.1.2

POWER-ON RESET

The on-chip Power-on reset initializes the chip after

power-on or power failure.

5.1.3

I2C-BUS CONTROLLER

The I2C-bus controller detects the I2C-bus protocol, slave

address, commands and display data bytes. It performs

the conversion of the data input (serial-to-parallel).

The PCF8535 acts as an I2C-bus slave and therefore

cannot initiate bus communication.

5.1.4

INPUT FILTERS

Input filters are provided to enhance noise immunity in

electrically adverse environments; RC low-pass filters are

provided on the SDA, SCL and RES lines.

5.1.5

DISPLAY DATA RAM

The PCF8535 contains a 65

× 133 bit static RAM which

stores the display data. The RAM is divided into 9 banks of

133 bytes. The last bank is used for icon data and is only

one bit deep. During RAM access, data is transferred to

the RAM via the I2C-bus interface. There is a direct

correspondence between the X address and the column

output number.

5.1.6

TIMING GENERATOR

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the data bus.

5.1.7

ADDRESS COUNTER

The Address Counter (AC) sends addresses to the Display

Data RAM (DDRAM) for writing.

5.1.8

DISPLAY ADDRESS COUNTER

The display is generated by continuously shifting rows of

RAM data to the dot matrix LCD via the column outputs.

The display status (all dots on or off, normal or inverse

video) is set via the I2C-bus.

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