PCF8535 datasheet(7/52 Pages) PHILIPS

7 / 52 page

1999 Aug 24

Philips Semiconductors

Objective speciﬁcation

× 133 pixel matrix driver

PCF8535

6.1.2

C0 TO C132

These pads output the display column signals.

6.1.3

VSS1 AND VSS2

VSS1 and VSS2 must be connected together.

6.1.4

VDD1 TO VDD3

VDD1 is the logic supply. VDD2 and VDD3 are for the voltage

multiplier. For split power supplies VDD2 and VDD3 must be

connected together. If only one supply voltage is available,

all three supplies must be connected together.

6.1.5

VLCDOUT

If, in the application, an external VLCD is used, VLCDOUT

must be left open-circuit; otherwise (if the internal voltage

multiplier is enabled) the chip may be damaged. VLCDOUT

should not be driven when VDD1 is below its minimum

allowed value otherwise a low impedance path between

VLCDOUT and VSS1 will exist.

6.1.6

VLCDIN

This is the VLCD supply for when an external VLCD is used.

If the internal VLCD generator is used, then VLCDOUT and

VLCDIN must be connected together. VLCDIN should not be

driven when VDD1 is below its minimum allowed value,

otherwise a low impedance path between VLCDIN and VSS1

will exist.

6.1.7

VLCDSENSE

This is the input to the internal voltage multiplier regulator.

It must be connected to VLCDOUT when the internal voltage

generator is used otherwise it may be left open-circuit.

VLCDSENCE should not be driven when VDD1 is below its

minimum allowed value, otherwise a low impedance path

between VLCDSENCE and VSS1 will exist.

6.1.8

SDA

I2C-bus serial data input.

6.1.9

SDAOUT

SDAOUT is the serial data acknowledge for the I2C-bus.

By connecting SDAOUT to SDA externally, the SDA line

becomes fully I2C-bus compatible. Having the

acknowledge output separated from the serial data line is

advantageous in Chip-On-Glass (COG) applications.

In COG applications where the track resistance from the

SDAOUT pad to the system SDA line can be significant, a

potential divider is generated by the bus pull-up resistor

and the Indium Tin Oxide (ITO) track resistance. It is

possible that during the acknowledge cycle the PCF8535

will not be able to create a valid logic 0 level. By splitting

the SDA input from the SDAOUT output the device could

be used in a mode that ignores the acknowledge bit.

In COG applications where the acknowledge cycle is

required or where read back is required, it is necessary to

minimize the track resistance from the SDAOUT pad to the

system SDA line to guarantee a valid LOW level.

6.1.10

SCL

I2C-bus serial clock input.

6.1.11

SA0 AND SA1

Least significant bits of the I2C-bus slave address.

Table 1

Slave address; see note 1

Note

1. The slave address is a concatination of the following

bits {01111, SA1, SA0 and R/W}.

6.1.12

OSC

If the on-chip oscillator is used this input must be

connected to VDD1 or VSS1.

6.1.13

RES

External reset pad: when this pad is LOW the chip will be

reset; see Section 7.1. If an external reset is not required,

this pad must be tied to VDD1. Timing for the RES pad is

given in Chapter 12.

6.1.14

T1, T2, T3, T4 AND T5

In applications T4 and T5 must be connected to VSS.

T1, T2 and T3 are to be left open-circuit.

SA1 AND SA0

MODE

SLAVE ADDRESS

0 and 0

write

78H

read

79H

0 and 1

write

7AH

read

7BH

1 and 0

write

7CH

read

7DH

1 and 1

write

7EH

read

7FH

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