PCF8535 datasheet(24/52 Pages) PHILIPS

24 / 52 page

1999 Aug 24

Philips Semiconductors

Objective speciﬁcation

× 133 pixel matrix driver

PCF8535

7.16

Instruction set

Data accesses to the PCF8535 can be broken down into

two areas, those that define the operating mode of the

device and those that fill the display RAM; the distinction

being the D/C bit. When the D/C bit is at logic 0, the chip

will respond to instructions as defined in Table 16. When

the D/C bit is at logic 1, the chip will store data into the

RAM. Data may be written to the chip that is independent

to the presence of the display clock.

There are 4 instruction types. Those which:

1. Define PCF8535 functions such as display

configuration, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

In normal use, category 3 instructions are the most

frequently used. To lessen the MPU program load,

automatic incrementing by one of the internal RAM

address pointers after each data write is implemented.

The instruction set is broken down into several pages,

each command page being individually addressed via the

H[2:0] bits.

7.16.1

RAM READ/WRITE COMMAND PAGE

This page is special in that it is accessible independently

of the H bits. This page is mainly used as a stepping stone

to other pages. Sending the ‘Default H[2:0]’ command will

cause an immediate step to the ‘Function and RAM

command page’ which will allow the H[2:0] bits to be set.

7.16.2

FUNCTION AND RAM COMMAND PAGE

7.16.2.1

Command page

Setting H[2:0] will move the user immediately to the

required command page. Pages not listed should not be

accessed as the behaviour is not defined.

7.16.2.2

Function set

When PD = 1, the LCD driver is in power-down mode:

• All LCD outputs at VSS

• Oscillator off

• VLCDIN may be disconnected

• I2C-bus interface accesses are possible

• RAM contents are not cleared; RAM data can be written

• Register settings remain unchanged.

When V = 0, horizontal addressing is selected. When

V = 1, vertical addressing is selected. The behaviour is

described in Section 7.15.

7.16.2.3

RAM page

The XM0 bit extends the RAM into a second page. The bit

may be considered to be the Most Significant Bit (MSB) of

an 8-bit X address. The behaviour is described in

Section 7.15.

7.16.2.4

Set Y address

The Y address is used as a pointer to the RAM for RAM

writing. The range is 0 to 8. Each bank corresponds to a

set of 8 rows, the only exception being bank 8, which

contains the icon data and is only 1-bit deep; see Table 13.

Table 13 Y address pointer

Y[3]

Y[2]

Y[1]

Y[0]

BANK

ROWS

0000

bank 0

R0 to R7

0001

bank 1

R8 to R15

0010

bank 2

R16 to R23

0011

bank 3

R24 to R31

0100

bank 4

R32 to R39

0101

bank 5

R40 to R47

0110

bank 6

R48 to R55

0111

bank 7

R56 to R63

1000

bank 8

(icons)

R64

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