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PCF2105MU/2 датащи(PDF) 28 Page - NXP Semiconductors |
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PCF2105MU/2 датащи(HTML) 28 Page - NXP Semiconductors |
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28 / 48 page ![]() 1998 Jul 30 28 Philips Semiconductors Product specification LCD controller/driver PCF2105 Notes 1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive; internal or external clock with duty factor 50%. 2. Resets all logic when VDD <VPOR. 3. When the voltages are above VDD or below VSS, an input current may flow; this current must not exceed ±0.5 mA. 4. Tested on sample basis. 5. Resistance of output terminals (R32 to R1 and C60 to C1) with load current IL = 150 µA; VOP =VDD − VLCD =9V; outputs measured one at a time. 6. LCD outputs open-circuit. 15 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS =0V; VLCD =VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified. LCD outputs Ro(ROW) row output resistance on pads R32 to R1 note 5 − 1.5 3 k Ω Ro(COL) column output resistance on pads C60 to C1 note 5 − 36 k Ω Vbias(tol) bias voltage tolerance on pads R32 to R1 and C60 to C1 note 6 −±20 ±130 mV SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ffr(LCD) LCD frame frequency (internal clock) note 1 40 65 100 Hz fosc oscillator frequency (external clock) 90 150 225 kHz Bus timing characteristics: Parallel Interface; notes 1 and 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2105); see Fig.23 Tcy(en) enable cycle time 500 −− ns tW(en) enable pulse width 220 −− ns tsu(A) address set-up time 50 −− ns th(A) address hold time 25 −− ns tsu(D) data set-up time 60 −− ns th(D) data hold time 25 −− ns READ OPERATION (READING DATA FROM PCF2105 TO MICROCONTROLLER); see Fig.24 Tcy(en) enable cycle time 500 −− ns tW(en) enable pulse width 220 −− ns tsu(A) address set-up time 50 −− ns th(A) address hold time 25 −− ns td(D) data delay time −− 150 ns th(D) data hold time 20 − 100 ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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