PCF2105MUSLASH2 datasheet(7/48 Pages) PHILIPS

7 / 48 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

LCD controller/driver

PCF2105

8.8

Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data,

represented by 8-bit character codes. DDRAM locations

not used for storing display data can be used as general

purpose RAM. The basic DDRAM-to-display mapping

scheme is shown in Fig.2. With no display shift, the

characters represented by the codes in the first

12 or 24 DDRAM locations, starting at address 00 in

line 1, are displayed. Subsequent lines display data

starting at addresses 20, 40, or 60 hexadecimal (hex).

Figures 3 and 4 show the DDRAM-to-display mapping

scheme when the display is shifted.

The address range for a 1-line display is 00 to 4F; for a

2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);

for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and

60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and

4-line displays the end address of one line and the start

address of the next line are not successive. When the

display is shifted each line wraps around independently of

the others (see Figs 3 and 4).

When data is written to the DDRAM, wrap-around occurs

from 4F to 00 in 1-line display and from 27 to 40 and

67 to 00 in 2-line display; from 13 to 20, 33 to 40, 53 to 60

and 73 to 00 in 4-line display.

8.9

Character Generator ROM (CGROM)

The CGROM generates 240 character patterns in 5

× 8

dot format from 8-bit character codes. Figure 5 shows the

character set currently available.

8.10

Character Generator RAM (CGRAM)

Up to 16 user-defined characters may be stored in the

CGRAM. The CGROM and CGRAM use a common

address space, of which the first column is reserved for the

CGRAM (see Fig.5). Figure 6 shows the addressing

principle for the CGRAM.

8.11

Cursor control circuit

The cursor control circuit generates the cursor (underline

and/or character blink as shown in Fig.7) at the DDRAM

address contained in the address counter. When the

address counter contains the CGRAM address the cursor

will be inhibited.

8.12

Timing generator

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the data buses.

8.13

LCD row and column drivers

The PCF2105 contains 32 row drivers and 60 column

drivers. They connect the appropriate LCD bias voltages in

sequence to the display, in accordance with the data to be

displayed. The bias voltages and the timing are selected

automatically when the number of lines in the display is

selected. Figures 8 and 9 show typical waveforms.

In the 1-line display (MUX rate 1 : 16), the row outputs are

driven in pairs, for example R1/R17 and R2/R18.

This allows the output pairs to be connected in parallel,

thereby providing greater drive capability.

Unused outputs should be left unconnected.

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