PCF2105MUSLASH2 datasheet(22/48 Pages) PHILIPS

22 / 48 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

LCD controller/driver

PCF2105

11 INTERFACE TO MICROCONTROLLER (I2C-BUS

INTERFACE)

11.1

Characteristics of the I2C-bus

The I2C-bus is for bidirectional, 2-line communication

between different ICs or modules. The 2 lines are a serial

data line (SDA) and a serial clock line (SCL). Both lines

must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

11.2

Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH-level period of the clock pulse as changes in the

data line at this time will be interpreted as a control signal

(see Fig.16).

11.3

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P) (see Fig.17).

11.4

System conﬁguration

A device generating a message is a transmitter, a device

receiving a message is the receiver. The device that

controls the message is the master and the devices which

are controlled by the master are the slaves (see Fig.18).

11.5

Acknowledge

The number of data bytes transferred between the START

and STOP conditions from transmitter to receiver is

unlimited. Each byte of 8 bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH signal put

on the bus by the transmitter during which time the master

generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. Also a

master receiver must generate an acknowledge after the

reception of each byte that has been clocked out of the

slave transmitter. The device that acknowledges must

pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse (set-up and

hold times must be taken into consideration). A master

receiver must signal an end of data to the transmitter by

not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition (see Fig.19).

11.6

I2C-bus protocol

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

start procedure. The I2C-bus configuration for the different

PCF2105 read and write cycles is illustrated in

Figs 20, 21 and 22.

Fig.16 Bit transfer.

handbook, full pagewidth

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

PCF2105MU/2 датащи(PDF) 22 Page - NXP Semiconductors

PCF2105MU/2 датащи(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL