VT6306 datasheet(13/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-7-

Pinouts

Pin Descriptions

Table 1. Pin Descriptions

PCI Bus Interface

Signal Name

Pin #

I/O

Signal Description

AD[31:0]

97-101, 104-106,

109-110, 112,

116-120, 5-7,

10-14, 17-19,

21-23, 27-28

Address / Data Bus.

The standard PCI address and data lines. The address is driven

with FRAME# assertion and data is driven or received in following cycles.

CBE[3:0]#

107, 122, 4, 15

Command / Byte Enable.

The command is driven with FRAME# assertion. Byte

enables corresponding to supplied or requested data are driven on following clocks.

FRAME#

123

Frame.

Assertion indicates the address phase of a PCI transfer. Negation indicates

that one more data transfer is desired by the cycle initiator.

DEVSEL#

127

Device Select.

As an output, this signal is asserted to claim PCI transactions through

positive or subtractive decoding. As an input, DEVSEL# indicates the response to a

VT6306-initiated transaction and is also sampled when decoding whether to

subtractively decode the cycle.

TRDY#

126

Target Ready.

Asserted when the target is ready for data transfer.

IRDY#

124

Initiator Ready.

Asserted when the initiator is ready for data transfer.

PREQ#

PCI Bus Request.

Asserted by the bus master to indicate to the bus arbiter that it

wants to use the bus.

PGNT#

PCI Bus Grant.

Asserted to indicate that access to the bus is granted.

IDSEL

108

Initialization Device Select.

IDSEL is used as a chip select during configuration

read and write cycles.

INTA#

Interrupt.

An asynchronous signal used to request an interrupt.

PCICLK

PCI Clock.

Timing reference for all transactions on the PCI Bus.

PCIRST#

Reset.

When detected low, an internal hardware reset is performed. PCIRST#

assertion or deassertion may be asynchronous to PCLK, however, it is recommended

that deassertion be synchronous to guarantee a clean and bounce free edge.

PAR

Parity.

A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

PERR#

Parity Error.

Parity error is asserted when a data parity error is detected.

STOP#

128

Stop.

Asserted by the target to request the master to stop the current transaction.

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