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We Connect

Technologies,Inc.

VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

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Table of Contents

TABLE OF CONTENTS

REVISION HISTORY ....................................................................................................................................................................... I

TABLE OF CONTENTS ..................................................................................................................................................................II

LIST OF FIGURES AND TABLES............................................................................................................................................... IV

OVERVIEW .......................................................................................................................................................................................3

PINOUTS ............................................................................................................................................................................................5

PIN DIAGRAM.................................................................................................................................................................................5

PIN LIST..........................................................................................................................................................................................6

PIN DESCRIPTIONS.........................................................................................................................................................................7

REGISTERS .....................................................................................................................................................................................12

REGISTER OVERVIEW..................................................................................................................................................................12

PCI Function 0 Registers – Link Controller.......................................................................................................................12

Memory-Space Registers – Link Controller .......................................................................................................................13

PHY Registers .......................................................................................................................................................................15

REGISTER DESCRIPTIONS............................................................................................................................................................16

Link Controller Configuration Registers (PCI Function 0) ..............................................................................................16

Configuration Space Header ..................................................................................................................................................................16

Controller-Specific Configuration Registers..........................................................................................................................................18

Power Management Registers................................................................................................................................................................19

Link Controller Memory-Space Registers ..........................................................................................................................20

Autonomous CSR Resources .................................................................................................................................................................21

Bus Management CSR Registers ...........................................................................................................................................................21

HC Control Registers.............................................................................................................................................................................23

Self-ID Control Registers ......................................................................................................................................................................24

Channel Mask Registers ........................................................................................................................................................................24

Interrupt Registers..................................................................................................................................................................................25

Link Control Registers...........................................................................................................................................................................27

PHY Control Registers ..........................................................................................................................................................................28

Cycle Timer Registers............................................................................................................................................................................28

Filter Registers.......................................................................................................................................................................................29

Asynchronous Transmit & Receive Context Registers ..........................................................................................................................30

Isochronous Transmit Context Registers ...............................................................................................................................................32

Isochronous Receive Context Registers.................................................................................................................................................33

PHY Registers .......................................................................................................................................................................35

PHY Register Overview.........................................................................................................................................................................35

PHY Register Bit Field Descriptions .....................................................................................................................................................35

PHY Register Page 0 - Port Status.........................................................................................................................................................36

PHY Register Page 1 - Vendor Identification........................................................................................................................................37

PHY Register Page 7 - Vendor-Dependent............................................................................................................................................37

FUNCTIONAL DESCRIPTIONS...................................................................................................................................................38

PHY GENERAL DESCRIPTION.....................................................................................................................................................38

Cable Interface ......................................................................................................................................................................38

PHY CIRCUIT DESCRIPTION.......................................................................................................................................................39

Pinless PLL and Clock Generation......................................................................................................................................39

Power Down and Auto Power Save .....................................................................................................................................39

Pinless PHY RESET .............................................................................................................................................................39

Data Transmission ................................................................................................................................................................39