VT6306 datasheet(46/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-40-

Functional Descriptions

a port in a low power state is capable of detecting connection status changes and detecting incoming TPBIAS. When all three ports

are suspended, all circuits except the connect-detect circuits and bias-detect circuits are powered down, resulting in significant

power savings. The connect-detect circuit monitors the value of incoming TPA pair common-mode voltage when local TPBIAS is

inactive. A very small current source charges the XTPBIAS pin to almost VCC when the cable is not connected. Before the

connect-detect circuit is enabled, the VT6306 enables a bias-discharger to improve the later-on connect-detect quality. Both the

cable bias-detect monitor and connect-detect monitor are used in connect / suspend / resume / disable signaling. For additional

details of suspend / resume / disable operation, refer to the IEEE P1394a V4.0 specification.

Twisted-Pair TPA and TPB

The line drivers operate in a high-impedance current mode, and are designed to work with external 110 Ohm line-termination

resistor networks in order to match the 110 Ohm cable impedance. One network is provided at each end of all twisted-pair cable.

Each network is composed of a pair of series-connected 55 Ohm resistors. The midpoint of the pair of resistors that is directly

connected to the twisted-pair TPA pins is connected to its corresponding XTPBIAS pin. The midpoint of the pair of resistors that is

directly connected to the twisted-pair B pins is coupled to ground through a parallel RC network with recommended values of 5K

Ohm and 270 pF. The values of the external line termination resistors are designed to meet the standard specifications when

connected in parallel with the internal receiver circuits.

Bandgap Current Generation

An external resistor connected between the XRES pin and ground sets the driver output current, as well as internal operating

currents. This current setting resistor has a value of 6.34K Ohm +/- 1%.

Power Off

When the power supply of the VT6306 is removed while the twisted-pair cables are connected, the VT6306 transmitter / receiver

circuitry and the XTPBIAS pin presents a high impedance state. As the consequence, peer PHYs see the VT6306 as unconnected.

Unimplemented Ports

When the VT6306 is used with one or more of the ports not brought out to a connector, some of the twisted-pair pins of the unused

ports can be left unconnected to reduce implementation cost. For each unused port, the XTPBIAS pins can be tied to analog power

(VCCA) for more reliable operation. The XTPAP, XTPAM, XTPBP and XTPBM pins of an unused port can be left unconnected.

CMC, PC0, PC1, PC2 Strapping

CMC and PC[0:2] are used as strapping pins to set the default value for four configuration status bits in the self-ID packet and

should be hard-wired high or low as a function of the equipment design. The PC0, PC1, and PC2 pins are used to indicate the

default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 7

below for power class encoding. The CMC pin is used as an input to indicate that the node is a contender for bus manager.

Table 7. Power Class Pin Strapping

PC[0:2] Power Consumption and Source Characteristics

000b

Node does not need power and does not repeat power

001b

Node is self-powered and provides a minimum of 15W to the bus

010b

Node is self-powered and provides a minimum of 30W to the bus

011b

Node is self-powered and provides a minimum of 45W to the bus

100b

Node may be powered from the bus and is using up to 1W

101b

Node is powered from the bus and is using up to 1W. An additional 2W is needed to enable the link and higher layers.

110b

Node is powered from the bus and is using up to 1W. An additional 5W is needed to enable the link and higher layers.

111b

Node is powered from the bus and is using up to 1W. An additional 9W is needed to enable the link and higher layers.

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