VT6306 datasheet(8/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-2-

Features

•••• Integrated 400 Mbit 3-Port PHY

− Supports provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the P1394a Supplement 4.0.

− Fully interoperable with IEEE Std 1394-1995 devices

− Full P1394a Supplement Support includes:

− Arbitrated short reset,

− Enhanced priority arbitration,

− Connection debounce,

− Multispeed packet concatenation,

− Ack accelerated arbitration,

− Fly-by concatenation,

− Per port disable, suspend, resume, through register write and remote command packet,

− Remote access packet

− Boundary node short reset

− No phy_ID wrap past 63

− −Provides three 1394a fully compliant cable ports at 100/200/400 Mbit per second

− Host notification of PHY LinkOn events

− Logic performs bus initialization and arbitration functions

− Encode and decode functions included for data-strobe bit-level encoding

− Incoming data resynchronized to local clock.

− 24.576 MHz crystal oscillator and PLL provide TX/RX data at 100/200/400 Mbps and Link-Layer Controller clock

at 49.152 MHz.

− Cable power presence monitoring.

− Programmable node power class information for system power management

− Fully Compliant P1394a 4.0 PHY register map

− Separate TPBIAS for each port

− Cable ports monitor line conditions for active connection to remote node

− Automatic power down inactive circuit and logic for low power application

− Self power up reset and pinless PLL to reduce passive component counts on system

− Automatic configuration to single-port, two-port, and three-port applications; unused ports power down

automatically

− Dedicated power supply pins separate from link core

− 2KV ESD protection

•••• 3.3V Power Supply with 5V Tolerant Inputs

•••• 0.35um, Low Power CMOS Process

•••• 128-Pin PQFP Package (VT6306) and 128-Pin LQFP Package (VT6306L) Available

•••• PCB Reference Designs & Schematics Available

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