VT6306 datasheet(39/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-33-

Isochronous Receive Context Registers

Offset 400 (Set), 404 (Clr) – Isoch Rcv Context 0 .......... RW

Offset 420 (Set), 424 (Clr) – Isoch Rcv Context 1 .......... RW

Offset 440 (Set), 444 (Clr) – Isoch Rcv Context 2 .......... RW

Offset 460 (Set), 464 (Clr) – Isoch Rcv Context 3 .......... RW

Offset 480 (Set), 484 (Clr) – Isoch Rcv Context 4 .......... RW

Offset 4A0 (Set), 4A4 (Clr) – Isoch Rcv Context 5 ........ RW

Offset 4C0 (Set), 4C4 (Clr) – Isoch Rcv Context 6 ........ RW

Offset 4E0 (Set), 4E4 (Clr) – Isoch Rcv Context 7......... RW

These registers are the Context Control registers for

isochronous Receive Contexts 0-3. Each context consists of

three registers:

a Command Pointer, a Context Control

is used by software to tell the controller where the context

program begins.

The Context Control register controls the

context’s behavior and indicates current status. The Context

Match Register is used to start transmitting from a context

program on a specified cycle number. The bit layout for the

Context Control registers is given below:

Buffer Fill

Each received packet is placed in a single

buffer

Received packets are placed back-to-back to

completely fill each receive buffer

If the “Multi-Channel Mode” bit is set, this bit must

also be set. This bit must not be changed while the

“Active” bit is set.

Isoch Header

The packet header is stripped from received

isochronous packets

Received packets will include the isochronous

packet header (the header will be stored first in

memory followed by the payload). The end of

the packet will be marked with a “Transfer

Status” (bits 15-0 of this register) in the first

word

followed

by a

16-bit time

stamp

indicating the time of the most recently

received “Cycle Start” packet.

Cycle Match Enable

Context will begin running immediately

Context will begin running only when the 13-

bit “Cycle Match” field in the “Context

Match” register matches the 13-bit “Cycle

Count” in the Cycle Start packet.

The effects of this bit are impacted by the values of

other bits in this register. Once the context becomes

active, this bit is cleared automatically by the chip.

Multi-Channel Mode

The context will receive packets for a single

channel.

The context will receive packets for all

isochronous channels enabled in the “IR

Channel Mask High” and “IR Channel Mask

Low” registers (the channel number in the

“Context Match” register is ignored). If more

than one Context Control register has the

Multi-Channel

Mode

bit

set,

unspecified

behavior will result.

27-16 Reserved

........................................always reads 0

Run

This bit is set and cleared by software to enable

descriptor processing for a context.

The chip will

clear this bit automatically on a hardware or software

reset. Before software sets this bit, the active bit must

be clear and the Command Pointer register for the

context must contain a valid descriptor block address

and a Z value that is appropriate for the descriptor

block address.

Software may stop the chip from further processing of

a context by clearing this bit. When cleared, the chip

will stop processing of the context in a manner that

will not impact the operation of any other context or

DMA controller.

This may require a significant

amount of time. If software clears the run bit while

the chip is processing a packet for the context, it will

continue to receive or transmit the packet and update

descriptor status. It will then stop at the conclusion

of that packet.

Clearing the bit may have other side effects that are

DMA controller dependent. This is described in the

sections that cover each of the DMA controllers.

14-13 Reserved

........................................always reads 0

Wake

..............................................default = 0

When software adds to a list of descriptors for a

context, the chip may have already read the descriptor

that was at the end of the list before it was updated.

This bit provides a semaphore to indicate that the list

may have changed.

If the chip had fetched a descriptor and the indicated

branch address had a Z value of zero, it will reread

the pointer value when the wake bit is set. If, on the

reread, the Z value is still zero, then the end of the list

has been reached and the chip will clear the active bit.

If, however, the Z value is now non-zero, the chip

will continue processing. If the wake bit is set while

the chip is active and has a Z value of non-zero, it

takes no special action.

The chip will clear this bit before it reads or rereads a

descriptor. The wake bit should not be set while the

run bit is zero.

Dead

..............................................default = 0

This bit is set by the chip to indicate a fatal error in

processing a descriptor. When set, the active bit is

cleared. This bit is cleared when software clears the

run bit or on a hardware or software reset.

Active

..............................................default = 0

This bit is set by the chip when software sets the run

bit or sets the wake bit while the run bit is set. The

chip will clear this bit:

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