PCD3316 datasheet(20/30 Pages) PHILIPS

20 / 30 page

Philips Semiconductors

PCD3316

CIDCW receiver

Product speciﬁcation

11 March 1999

20 of 30

9397 750 04824

[1]

Except for FSK and CAS detection, all circuitry works already when VDD >VPOR(H). Since the I2C-bus interface will work (starts to

acknowledge), the application can start reading the LOW-BAT Indication bit (Status register, bit 5) to check whether the supply voltage

has reached the operating voltage level. A voltage divider network can be connected to pins VDD, LOWBAT and AGND/DGND such that

VLOWBAT =Vref if VDD =VDD(min).

[2]

The power-on reset LOW level is deﬁned as VPOR(L) =VPOR(H) − Vhys(POR). By design VPOR(L) is always lower than VPOR(H).

[3]

32 kHz oscillator on (MIN Interrupt, SEC Interrupt, Polarity change, Low battery and Level detect available).

[4]

3.58 MHz oscillator on (device fully operational).

[5]

GND < VI <VDD. The leakage currents are generally very small, <1 nA. The value given here, 1 µA, is a maximum that can occur after

an Electrostatic Stress on the pin.

[6]

When FSK is selected the signal power is measured between 1000 and 2200 Hz. When CAS is selected signal levels are measured

between 2000 and 2800 Hz.

[7]

The IRQ pin is implemented as a 3-state pin which is only active (either HIGH or LOW) when an interrupt occurs. A pull-up or pull-down

has to be connected to deﬁne the line when no interrupt is generated.

[8]

Veriﬁed on sampling basis.

[9]

According to Bellcore speciﬁcation: near end speech level

≤−7 dBm ASL (ASL = Active Speech Level), referenced to 600 Ω, according

to method B of recommendation P.56.

[10] Pins SCL and SDA are equipped with an open-drain output buffer. The pins have no clamp diode to VDD.

[11] The input threshold voltage of SCL and SDA meet the I2C-bus speciﬁcation. Therefore, an input voltage below 0.3VDD will be recognized

as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1

[12] Maximum capacitive load for each bus line is 400 pF.

[13] C1i and C2i are the total internal capacitances (including gate capacitance and leadframe capacitance).

3.58 MHz oscillator (pins HXIN and HXOUT)

VHXIN(p-p)

external clock signal amplitude

(peak-to-peak value) on pin HXIN

0.5

−

VDD

Zi(HXIN)

input impedance on pin HXIN

300

1000

−

Ω

C1i; C2i

input capacitance on pins HXIN and

HXOUT [13]

−

32 kHz oscillator (pins LXIN and LXOUT)

transconductance

Vi(p-p) <50mV

µS

Ci(LXIN)

LXIN input capacitance

−

Co(LXOUT)

LXOUT output capacitance

−

Table 18: Characteristics…continued

VDD = 2.5 to 3.6 V; Tamb = −25 to +70 °C; HXIN = 3.579545 MHz ±0.05%; LXIN = 32.768 kHz ±0.1%; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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