Philips Semiconductors

PCD3316

CIDCW receiver

Product specification

11 March 1999

7 of 30

9397 750 04824

© Philips Electronics N.V. 1999. All rights reserved.

The 32.768 kHz clock signal must be available. The LOW-BAT Indication bit does not

generate interrupts, thus the bit should be polled.

7.6 Level detect

When the input signal level on the FSK or the CAS input (the one that is selected) is

below a threshold of typically

−40 dBm, the Low Level Status bit will be set (Interrupt

register, bit 4). The level detector can be used to observe a carrier loss during FSK

transmission and to detect the ‘Idle State Tone Alert Signal’ for British Telecom. The

signal power on the input can be monitored by polling the register bit since it will not

generate an interrupt. Signal power is measured in a frequency band corresponding

to the selected operation mode, FSK (1000 to 2200 Hz) or CAS (2000 to 2800 Hz).

The Low Level Status bit will be updated every 8 ms. When FSK and CAS are both

disabled the signal level on the FSK input is measured. The 32.768 kHz clock signal

must be available.

7.7 Time base

The 32.768 kHz oscillator is used to generate either a 1 second or a 1 minute

interrupt signal. If the TB on/off bit is set (Mode register 2, bit 6) every second or

minute an interrupt is generated and MIN Interrupt and/or SEC Interrupt bits

(Interrupt register, bit 7 and 6) are set. After reading the Interrupt register the interrupt

is cleared.

The SEC/MIN (Mode register 2, bit 5) selects whether every second (SEC/MIN is set)

or every minute (SEC/MIN is cleared) an interrupt is generated. All possible

selections are shown in Table 3. Resetting bit TB on/off in Mode register 2 (bit 6) will

only disable time base interrupts, and the 32.768 kHz oscillator will continue to run.

7.8 Interrupt

The interrupt request output (IRQ) is active HIGH by default. The polarity of the IRQ

output can be made active LOW by the INT Polarity HIGH/LOW bit (Mode register 1,

bit 3). The IRQ pin is in 3-state when not active, so an external pull-up or pull-down

resistor is required. The interrupt cause is indicated by the flags in the Interrupt

register. Interrupt flags are set by hardware but must be reset by software. All flags of

The IRQ pin is deactivated at the positive edge of SCL which reads the first data bit of

the Interrupt register. The IRQ pin will stay inactive for one SCL cycle. IRQ can

handle a next interrupt after the next positive edge of SCL.

[1]

X = don’t care.

Table 3:

Selection of interrupt modes

Mode register 2 (CIDMD2)

Interrupt register (CIDINT)

Interrupt

TB on/off

(CIDMD2.6)

SEC/MIN

(CIDMD2.5)

MIN Interrupt

(CIDINT.7)

SEC Interrupt

(CIDINT.6)

0X [1]

0

0

no time base interrupt (time base is reset)

1

0

1

0

every minute an interrupt is generated; no second interrupt

1

1

1

1

every second an interrupt is generated; every minute an

interrupt is generated