Philips Semiconductors

PCD3316

CIDCW receiver

Product specification

11 March 1999

5 of 30

9397 750 04824

© Philips Electronics N.V. 1999. All rights reserved.

They can be used for ring or line polarity reversal detection. The POL on/off bit (Mode

register 1, bit 4) must be set to enable generation of an interrupt when a polarity

change occurs. The result of the two comparators can be read in bits 7 and 6 (POL0

and POL1) of the Status register (see Section 7.4). The 3.58 MHz clock is not needed

for the generation of a polarity interrupt.

7.2 CAS detection

After a power-on reset or after enabling the CAS detector the internal registers of the

CAS detection function are initialized. The initialization takes a maximum of

100 periods of the 3.58 MHz clock.

If the CAS detection is enabled the PCD3316 will generate an interrupt (Interrupt

register, bit 1 is set) when a correct dual tone (2130 and 2750 Hz) is detected.

Interrupts will be blocked when the signal level on the CAS input is below the

threshold in the level detector.

7.3 FSK reception

The FSK receiver function can be enabled by setting the FSK on/off bit (Mode

register 1, bit 7).

In the FSK transmission specification of BT and Bellcore a channel seizure is

transmitted first (sequence of 1010..). After the channel seizure a block of marks and

finally the data pattern are sent (see Figure 3). These mark bits are detected by the

PCD3316 which sets the FSK-BOM Indication bit (Status register, bit 4). The

FSK-BOM Indication bit is reset when the FSK receiver is disabled.

If the FSK-BOM Indication bit is set, the FSK receiver will generate an interrupt after it

has received a complete data word. An FSK data word consists of one start bit

(space), followed by eight data bits and one stop bit (mark). Interrupts will therefore

not be generated during the channel seizure and during the block of marks. When a

valid data word has been received, FSK data is available in the FSK data register.

By clearing the FSK-BOM-mask on/off bit (Mode register 1, bit 6), the FSK receiver

will not wait with the generation of interrupts until a Begin Of Mark (BOM) has been

detected but will handle the channel seizure as normal data. The block of marks

which is a string of logic 1 will still not generate interrupts because there are no start

bits.

After the generation of an interrupt the IRQ pin will become active (see Figure 4), and

the FSK Interrupt bit is set (Interrupt register, bit 5). The received data is available in

the FSK data register.

Fig 3.

FSK transmission specification.

width

MBH979

channel seizure

mark

FSK transmission

FSK-BOM

data