AM29LV640MT100REF datasheet(15/66 Pages) AMD

15 / 66 page

February 1, 2007 26190C8

Am29LV640MT/B

D A TA

SH EET

vice is in either of these standby modes, before it is

ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

See the table in DC Characteristics on page 43 for the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Refer to the DC Characteristics table for the automatic

sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP, the

device immediately ter minates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. To ensure data integrity,

reinitiate the operation that was interrupted, once the

device is ready to accept another command se-

quence.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS±0.3 V, the device

draws CMOS standby current (I

CC4). If RESET# is held

at V

IL but not within VSS±0.3 V, the standby current is

greater.

The RESET# pin can be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2.

Am29LV640MT Top Boot Sector Architecture

Sector

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

0000000xxx

64/32

000000h–00FFFFh

00000h–07FFFh

SA1

0000001xxx

64/32

010000h–01FFFFh

08000h–0FFFFh

SA2

0000010xxx

64/32

020000h–02FFFFh

10000h–17FFFh

SA3

0000011xxx

64/32

030000h–03FFFFh

18000h–1FFFFh

SA4

0000100xxx

64/32

040000h–04FFFFh

20000h–27FFFh

SA5

0000101xxx

64/32

050000h–05FFFFh

28000h–2FFFFh

SA6

0000110xxx

64/32

060000h–06FFFFh

30000h–37FFFh

SA7

0000111xxx

64/32

070000h–07FFFFh

38000h–3FFFFh

SA8

0001000xxx

64/32

080000h–08FFFFh

40000h–47FFFh

SA9

0001001xxx

64/32

090000h–09FFFFh

48000h–4FFFFh

SA10

0001010xxx

64/32

0A0000h–0AFFFFh

50000h–57FFFh

SA11

0001011xxx

64/32

0B0000h–0BFFFFh

58000h–5FFFFh

SA12

0001100xxx

64/32

0C0000h–0CFFFFh

60000h–67FFFh

SA13

0001101xxx

64/32

0D0000h–0DFFFFh

68000h–6FFFFh

SA14

0001101xxx

64/32

0E0000h–0EFFFFh

70000h–77FFFh

SA15

0001111xxx

64/32

0F0000h–0FFFFFh

78000h–7FFFFh

SA16

0010000xxx

64/32

100000h–00FFFFh

80000h–87FFFh

SA17

0010001xxx

64/32

110000h–11FFFFh

88000h–8FFFFh

SA18

0010010xxx

64/32

120000h–12FFFFh

90000h–97FFFh

SA19

0010011xxx

64/32

130000h–13FFFFh

98000h–9FFFFh

SA20

0010100xxx

64/32

140000h–14FFFFh

A0000h–A7FFFh

SA21

0010101xxx

64/32

150000h–15FFFFh

A8000h–AFFFFh

SA22

0010110xxx

64/32

160000h–16FFFFh

B0000h–B7FFFh

SA23

0010111xxx

64/32

170000h–17FFFFh

B8000h–BFFFFh

SA24

0011000xxx

64/32

180000h–18FFFFh

C0000h–C7FFFh

SA25

0011001xxx

64/32

190000h–19FFFFh

C8000h–CFFFFh

SA26

0011010xxx

64/32

1A0000h–1AFFFFh

D0000h–D7FFFh

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