AM29BDS640G datasheet(42/77 Pages) AMD

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Am29BDS640G

25903C2 May 9, 2006

Data

Sheet

RDY: Ready

The RDY is a dedicated output that, by default, indicates (when at logic low) the

system should wait 1 clock cycle before expecting the next word of data. Using

the RDY Configuration Command Sequence, RDY can be set so that a logic low

indicates the system should wait 2 clock cycles before expecting valid data.

RDY functions only while reading data in burst mode. The following conditions

cause the RDY output to be low: during the initial access (in burst mode), and

after the boundary that occurs every 64 words beginning with the 64th address,

3Fh.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address in the same bank, and is valid

after the rising edge of the final WE# pulse in the command sequence (prior to

the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. When the operation is complete, DQ6

stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 ms after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

See the following for additional information: Figure 4 (toggle bit flowchart), DQ6:

Toggle

Bit

(description),

Figure 28,

“Toggle

Bit

Timings

(During Embedded Algorithm),” on page 65 (toggle bit timing diagram), and

Table 14, “DQ6 and DQ2 Indications,” on page 42.

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