AM29BDS640G datasheet(34/77 Pages) AMD

34 / 77 page

Am29BDS640G

25903C2 May 9, 2006

Data

Sheet

The system must write the reset command to return to the read mode (or erase-

suspend-read mode if the bank was previously in Erase Suspend).

Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 13 shows the address and

data requirements for the program command sequence.

When the Embedded Program algorithm is complete, that bank then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the

“Write Operation Status” section on page 38 section for information on these sta-

tus bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program op-

eration. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit can-

not be programmed from “0” back to a “1.” Attempting to do so may cause that

bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the oper-

ation was successful. However, a succeeding read will show that the data is still

“0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to primarily program to a bank

faster than using the standard program command sequence. The unlock bypass

command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle unlock bypass program com-

mand sequence is all that is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program command, A0h; the second

cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required

Description

Address

Read Data

Manufacturer ID

(BA) + 00h

0001h

Device ID, Word 1

(BA) + 01h

227Eh

Device ID, Word 2

(BA) + 0Eh

2204h (1.8 V VIO, top boot),

2224h (1.8 V VIO, bottom boot),

2214h (3.0 V VIO, top boot),

2234h (3.0 V VIO, bottom boot)

Device ID, Word 3

(BA) + 0Fh

2201h

Sector Block

Lock/Unlock

(SA) + 02h

0001 (locked),

0000 (unlocked)

Handshaking

(BA) + 03h

43h (reduced wait-state),

42h (standard)

AM29BDS640G датащи(PDF) 34 Page - Advanced Micro Devices

AM29BDS640G датащи(HTML) 34 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL