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BL702/704/706 Datasheet

2.1 CPU

BL702/BL704/BL706 32-bit RISC CPU contains FPU (floating-point unit) for 32-bit single-precision arithmetic, three-

stage pipelined (IF, EXE, WB), compressed 16 and 32-bit instruction set, standard JTAG debugger port including 4

hardware-programmable breakpoints, interrupt controller including 64 interrupts and 16 interrupt levels/priorities for

low latency interrupt processing. Up to 144MHz clock frequency, can be dynamically configured to change clock

frequency, enter the power saving mode to achieve low power consumption.

Both zigBee/BLE stack and application run on single 32-bit RISC CPU for simple and ultra-low power applications.

CPU performance ~1.46 DMIPS/MHz. ~3.1 CoreMark/MHz.

2.2 Cache

BL702/BL704/BL706 cache improves CPU performance to access external memory. Cache memories can be partially

or fully configured as TCM (tightly coupled memory).

2.3 Memory

BL702/BL704/BL706 memories include: on-chip zero-delay SRAM memories, read-only memories, write-once memories,

embedded flash memory (optional), embedded pSRAM (BL704/BL706,optional).

2.4 DMA

BL702/BL704/BL706 DMA (direct memory access) controller has eight dedicated channels that manage data transfer

between peripherals and memories to improve cpu/bus efficiency.

There are four main types of transfers including memory to memory, memory to peripheral, peripheral to peripheral

and peripheral to memory. DMA also supports LLI (link list item) that multiple transfers are pre-defined by a series of

linked lists, then hardware automatically complete all transfers according to each LLI size and address. DMA supports

peripheral USB, UART, I2C, I2S, SPI, ADC and DAC.

2.5 Bus

BL702/BL704/BL706 bus fabric connection and memory-map summarized as follows：

Table 2.1: Bus Connectiom

Slave/ Master

CPU

Ethernet

DMA

Crypto

Engine

Debug

SRAM

Peripheral

BLE/zigbee

BL702/704/706 Datasheet

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