BL702/704/706 Datasheet

2.10.6 TIMER

The TIMER module contains two general-purpose timers and a watchdog timer. The clock source of the general-

purpose timer can be FCLK/32K/1K/XTAL, and the clock source of the watchdog timer can be FCLK/32K/XTAL. Each

The counter has an 8-bit frequency divider.

Each group of general-purpose timers contains three compare registers, supports compare interrupts, and count

mode supports FreeRun mode and PreLoad mode.

The bit width of the watchdog timer counter is 16 bits, and it supports two watchdog overflow modes: interrupt and

reset.

2.10.7 PWM

5-channel PWM interface, three kinds of clock sources BCLK/XCLK/32K can be selected, the bit width of the frequency

divider register is 16 bits, and the bit width of the period register is 16 bits. Supports adjustable output polarity and

dual threshold settings to increase the flexibility of pulse output. Support PWM cycle counting interrupt, used to count

the number of output pulses, etc.

2.10.8 IR(IR-remote)

One infrared remote control, supports two modes of generating and receiving, supports receiving data with fixed

protocols NEC and RC-5, and also supports receiving data in any format in pulse width counting mode.

The IR module clock source is XCLK, which has powerful infrared waveform editing capabilities and can send out

waveforms that conform to various protocols. The transmit power is adjustable in 15 levels, and the receive FIFO

depth can reach 64 bytes.

2.10.9 USB2.0(Full Speed)

Built-in a device controller compatible with full-speed USB, following the full-speed USB device standard, with 8

endpoints, each of which has a 64-byte deep FIFO, except for endpoint 0, all other endpoints support interrupt /batch

/synchronous transmission . With standby /resume function. The 48MHz clock dedicated to USB is directly generated

by the internal main PLL.

2.10.10 EMAC

EMAC is a 10/100Mbps Ethernet controller (Ethernet Media Access Controller) compatible with IEEE 802.3.

Compatible with the MAC layer functions defined by IEEE 802.3, support the PHY of the RMII interface defined by

IEEE 802.3, interact with the PHY through MDIO, support 10Mbps and 100Mbps Ethernet, support half-duplex and

full-duplex, data transmission and reception are realized through the Buffer Descriptor data structure .

EMAC control is embedded with AHB Master, which can read or write data directly from the memory. The Buffer

Descriptor data structure is stored in the internal RAM of EMAC. The total number of Buffer Descriptors is up to 128.

The user can flexibly configure the number of Buffer Descriptors for transmission and receiving according to the scene.

BL702/704/706 Datasheet

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