Table 3.2: GPIO Muxed Pins

Pin Name

Flash1

I2S

SPI

(Default

/SWAP=1)

CAM

UART2

(Default

/SWAP=1)

I2C

Master

PWM

Analog

External_PA

JTAG

(Default

/SWAP=1)

Ether_Mac

QDEC

Key_Scan_In

Key_Scan_Drive

IR

PAD_GPIO_22

SF1_IO2

DIO/DO

SS

-

SIG6

/SIG2

SCL

PWM_CH2

IRTX

FEM2

TCK/TMS

RMII_RX_DV

QDEC1_b

ROW6

COL2

IRRX

(ir_rx_gpio_sel=6)

PAD_GPIO_23

SF2_IO2

RCLK_O

/DI

SCLK

PIX_DAT4

SIG7

/SIG3

SDA

PWM_CH3

IRTX

FEM3

TDO/TDI

-

QDEC1_led

ROW7

COL3

IRRX

(ir_rx_gpio_sel=7)

PAD_GPIO_24

SF2_IO1

BCLK

MOSI

/MISO

PIX_DAT5

SIG0

/SIG4

SCL

PWM_CH4

-

FEM4

TMS/TCK

RMII_MDC

QDEC2_a

ROW0

COL4

IRRX

(ir_rx_gpio_sel=8)

PAD_GPIO_25

SF2_CS

FS

MISO

/MOSI

PIX_DAT6

SIG1

/SIG5

SDA

PWM_CH0

-

FEM0

TDI/TDO

RMII_MDIO

QDEC2_b

ROW1

COL5

IRRX

(ir_rx_gpio_sel=9)

PAD_GPIO_26

SF2_IO3

DIO/DO

SS

PIX_DAT7

SIG2

/SIG6

SCL

PWM_CH1

-

FEM1

TCK/TMS

RMII_RXERR

QDEC2_led

ROW2

COL6

IRRX

(ir_rx_gpio_sel=10)

PAD_GPIO_27

SF2_CLK

RCLK_O

/DI

SCLK

-

SIG3

/SIG7

SDA

PWM_CH2

-

FEM2

TDO/TDI

RMII_TX_EN

QDEC0_a

ROW3

COL7

IRRX

(ir_rx_gpio_sel=11)

PAD_GPIO_28

SF2_IO0

BCLK

MOSI

/MISO

PIX_DAT4

SIG4

/SIG0

SCL

PWM_CH3

-

FEM3

TMS/TCK

RMII_RX_DV

QDEC0_b

ROW4

COL8

IRRX

(ir_rx_gpio_sel=12)

PAD_GPIO_29

-

FS

MISO

/MOSI

PIX_DAT5

SIG5

/SIG1

SDA

PWM_CH4

-

FEM4

TDI/TDO

-

QDEC0_led

ROW5

COL9

IRRX

(ir_rx_gpio_sel=13)

PAD_GPIO_30

-

DIO/DO

SS

PIX_DAT6

SIG6

/SIG2

SCL

PWM_CH0

-

FEM0

TCK/TMS

-

QDEC1_a

ROW6

COL10

IRRX

(ir_rx_gpio_sel=14)

PAD_GPIO_31

-

RCLK_O

/DI

SCLK

PIX_DAT7

SIG7

/SIG3

SDA

PWM_CH1

-

FEM1

TDO/TDI

-

QDEC1_b

ROW7

COL11

IRRX

(ir_rx_gpio_sel=15)

1 There are 2 groups of Flash, and the smallest selection unit is group, which is configured according to group when used.

In Dual CS mode, PAD_GPIO_17 can be configured as SF2_CS2 function.

2 The default UART signal mapping table is shown below.