ES9842PRO datasheet(166/167 Pages) ESS

166 / 167 page

CONFIDENTIAL ADVANCE INFORMATION

ES9842 PRO Product Datasheet

166

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

• Updated Register 12-15[6:5] descriptions

• Added I2S decoder and Programmable delay section

• Updated Register Overview I2C table

• Updated Register 73 descriptions

0.2.1

April 14, 2021

• Updated Default value Register 13 [4:0] typo

• Updated GPIO section description

• Added Pin 41 Package pad description to Pin list

• Updated Register 87-86 mnemonics

0.2.3

May 10, 2021

• Updated Register 23 FS_PHASE description. Recommended to set to 7’d10

• Updated Register 11 [7] TDM_GPIO456

• Updated Device Markings

0.2.4

June 10, 2021

• Reserved register 73

• Added minimum MCLK frequency

0.3.1

October 15, 2021

• Added clock configuration tables

• Added 2x mode registers to clock distribution diagram

• Added reserved register note to top of register listings

• Added note on connecting package pin to DGND

• Major overall formatting changes

• Changed Standby power consumption

• Added Captions to all tables and figures

• Changed HP filter to DC blocking filter for clarity in Digital Path Block

diagram

• Re-organized Digital Features sub-sections and added corresponding

• Added Volume Control section under Digital Signal Path

• Updated GPIO section

• Added Addendum with s2m configurations

• Unreserved register 71

• Added PCM digital filter characteristics

• Updated IADC clock description

• Added ESD protection limits

• Corrected Figure 5 ES9311 pin names, pins 16-17, 24-25

• Updated ES9311 reference schematic

• Updated Register 64,66,68,70 descriptions

0.4

April 7, 2022

• Corrected Register Heading for register 23 (was an error)

• Updated power up and down sequencing

• Updated Register 6[5],192,193 Register Descriptions

• Added switching characteristics section

• Added audio interface timing requirements

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