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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ES9842PRO датащи(PDF) 36 Page - ESS Technology,Inc |
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ES9842PRO датащи(HTML) 36 Page - ESS Technology,Inc |
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36 / 167 page  CONFIDENTIAL ADVANCE INFORMATION ES9842 PRO Product Datasheet 36 VERSION 0.5 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM The following list shows the various clocks of the ES9842 PRO and the associated registers for configuration. Analog ADC Clock ADC clock must be maintained to be between 22.5792MHz & 24.576MHz • Register 194[0] (SEL_CLK_DIV) • Register 193[2:1] (SEL_SYSCLK_IN) • Register 193[0] (EN_ANA_CLKIN) IADC Clock (Digital Input ADC clock) Set to the same clock frequency as the analog ADC clock, digital sampling. • Register 3[2:0] (SELECT_IADC_NUM) o Set this so it matches Analog ADC clock of 22.5792 or 24.576MHz. • Register 1 o Dependent on channels required. • Register 193[2:1] (SEL_SYSCLK_IN) • Register 193[0] (EN_ANA_CLKIN) ADC Decimation Path Clock • Register 2[4:0] (SELECT_ADC_NUM) • Register 1 o Dependent on channels required. • Register 9[6:0] (SELECT_I2S_TDM_NUM) • Register 193[2:1] (SEL_SYSCLK_IN) • Register 193[0] (EN_ANA_CLKIN) Master BCK & WS • Register 8 • Register 7[7:5] MASTER_WS_SCALE • Register 9[6:0] SELECT_I2S_TDM_NUM • Register 193[2:1] (SEL_SYSCLK_IN) • Register 193[0] (EN_ANA_CLKIN) TDM Clock • Register 10[0] (ENABLE_TDM_CLK) S/PDIF Clock • Register 5[2] (ENABLE_SPDIF_CLK) |
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