ES9842PRO datasheet(35/167 Pages) ESS

35 / 167 page

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9842 PRO Product Datasheet

Clock Distribution

The ES9842 PRO includes features for selecting and manipulating the input clock source.

The minimum MCLK frequency is 22.579MHz.

When using 24.576 MHz or 22.579 MHz BCK, it is preferable to use GPIO4-6 as the data output.

• Register 74-91 (GPIOx/x_CONFIG) – set desired GPIO as AUX output and enable output mode.

• Register 12-15[6:5] (TDM_LINE_SEL_CHx) – change TDM Line Select to desired GPIO.

• Register 11[7] (TDM_GPIO456) – Enable TDM on GPIO456

XIN

XOUT

ACLK

System

Clock

(MCLK)

22-49MHz

Reg 194[1:0]

GPIO1

SCL_SLAVE

I2C/SPI Clock

BCK

Reg 1

Digital ADC

CLK DIV

Reg 2[4:0]

Reg 0[3]

ADC Decimation Path Clock

(128fs clock)

Reg 9[6:0]

Reg 8

Reg 7[7:5]

Master BCK

Master WS

Enable Reg 193[0]

Reg 193[2:1]

GPIO2

Reg 10[0]

TDM Clock

Reg 5[2]

S/PDIF Clock

Reg 35[0]

Reg 35[5:1]

CLK ASP1

Reg 36[0]

Reg 36[5:1]

CLK ASP2

Reg 6[3:0]

Reg 7[3:0]

CLK DSD

DIV2

Reg 7[4]

Digital

ADC

I2S Decoder

CLK DIV

Analog ADC Clock (Must be 22.5792MHz to 24.576 MHz)

Analog ADC

Clock

Gear

(1, ½)

Reg 3[2:0]

CLK IADC (digital Input ADC clock)

(Same frequency as Analog ADC clock)

CLK DIV

S/PDIF

Encoder

TDM

Encoder

Master

BCK/WS

Gen

Figure 10 - ES9842 PRO Clock Distribution

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