ES9842PRO datasheet(161/167 Pages) ESS

161 / 167 page

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9842 PRO Product Datasheet

161

Addendum

The following subsections outline the recommended configuration for Common I2S and TDM modes in s2m format.

I2S Master

FS=48kHz, 4 Channel from 2 data lines of I2S, MCLK=49.152MHz

w 0x48 193 0x01; //SEL_SYSCLK_IN = 00 (XTAL), EN_ANA_CLKIN = 1

//w 0x48 193 0x05; //SEL_SYSCLK_IN = 10 (ACLK), EN_ANA_CLKIN = 1

w 0x48 194 0x01; //SEL_CLK_DIV = 1/2 (sets ADC CLK rate, must be 22 or 24MHz)

w 0 0x00;

//OUTPUT_SEL = 00 (I2S)

w 2 0x07;

//SELECT_ADC_NUM = 7 for 48k/44.1k, 3 for 96k, 1 for 192k

w 3 0x01;

//SELECT_IADC_NUM = 1, should match SEL_CLK_DIV

w 8 0x07;

//MASTER_BCK_DIV1 = 0, MASTER_MODE_ENABLE = 1

w 9 0x07;

//SELECT_I2S_TDM_NUM = 7 for 48k/44.1k

w 10 0x05;

//TDM_VALID_EDGE = 1, ENABLE_TDM_CLK = 1

w 11 0x01;

//TDM_CH_NUM = 1 (# of channels = 1 + TDM_CH_NUM)

w 12 0x00;

//TDM_LINE_SEL_CH1: 00 (GPIO3),

TDM_SLOT_SEL_CH1: 0 (slot 0)

w 13 0x01;

//TDM_LINE_SEL_CH2: 00 (GPIO3),

TDM_SLOT_SEL_CH2: 1 (slot 1)

w 14 0x20;

//TDM_LINE_SEL_CH3: 01 (GPIO4),

TDM_SLOT_SEL_CH3: 0 (slot 0)

w 15 0x21;

//TDM_LINE_SEL_CH4: 01 (GPIO4),

TDM_SLOT_SEL_CH4: 1 (slot 1)

w 23 0x0A;

//FS_PHASE = 10

//GPIO enabling

w 74 0x22;

//GPIO1_CFG and GPIO2_CFG set to AUX output (master mode)

w 75 0x22;

//GPIO3 and GPIO4 set to AUX output

w 86 0x03;

//GPIO1_SDB and GPIO2_SDB input enabled (required)

w 88 0x0F;

//GPIO1_OE and GPIO2_OE and GPIO3_OE and GPIO4_OE output enabled

//ADC CONFIG

w 63 0xBB;

//adc ch1 config

w 64 0x38;

w 65 0xBB;

//adc ch2 config

w 66 0x38;

w 67 0xBB;

//adc ch3 config

w 68 0x38;

w 69 0xBB;

//adc ch4 config

w 70 0x38;

w 71 0xFF;

//set common mode to 3

//ADC filter and datapath registers

w 113 0x98; //ADC1_FILTER_SHAPE = Minimum phase slow roll off

w 130 0x98; //ADC2_FILTER_SHAPE = Minimum phase slow roll off

w 147 0x98; //ADC3_FILTER_SHAPE = Minimum phase slow roll off

w 164 0x98; //ADC4_FILTER_SHAPE = Minimum phase slow roll off

//Enable ADC

w 1 0xFF;

//ENABLE_ADC_CH and ENABLE_DATA_IN_CH

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