ES9842PRO datasheet(64/167 Pages) ESS

64 / 167 page

CONFIDENTIAL ADVANCE INFORMATION

ES9842 PRO Product Datasheet

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Some RESERVED registers do not default to 0x00 and should not be modified for normal operation. If the value of the

reserved registers is changed from the default state, it will be noted.

System Registers

Bits

[7]

[6:5]

[4]

[3]

[2]

[1]

[0]

Default

1'b0

2'b00

1'b0

Bits

Mnemonic

Description

[7]

SOFT_RESET

Performs soft reset to the digital core

• 1'b0: Normal operation

• 1'b1: Reset digital core

[6:5]

OUTPUT_SEL

Selects output data format.

• 2'd0: I2S output (default)

• 2'd1: SPDIF output

• 2'd2: TDM output

• 2'd3: DSD output

[4]

RESERVED

[3]

ENABLE_64FS_MODE

Enables 64FS mode for 768k sample rate.

• 1'b0: 64FS mode disabled (default)

• 1'b1: 64FS mode enabled

[2]

TWO_CH_MODE

Enables ADC two channel mode. ADC Channel 3 is mixed into ADC

Channel 1. ADC Channel 4 is mixed into Channel 2.

• 1'b0: Two channel mode disabled (default)

• 1'b1: Two channel mode enabled

[1]

MONO_MODE

Enables mono mode. All 4-channel data is mixed into Ch1. For Ch1,

mono mode has higher priority than two channel mode.

• 1'b0: Mono mode disabled (default)

• 1'b1: Mono mode enabled

[0]

RESERVED

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