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ES9826 датащи(PDF) 68 Page - ESS Technology,Inc

номер детали ES9826
подробное описание детали  32-bit High performance 2 Channel ADC w/PGA
PDF  88 Pages
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производитель  ESS [ESS Technology,Inc]
домашняя страница  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9826 датащи(HTML) 68 Page - ESS Technology,Inc

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ES9826 Datasheet
VERSION 0.1.2
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
68
Register 68: PGA GAIN CONTROL
Bits
[7:4]
[3:0]
Default
4'd0
4'd0
Bits
Mnemonic
Description
[7:4]
PGA_GAIN_SET_CH2
• If ARE is disabled, PGA_GAIN_SET_CH2 sets the amount of
PGA gain (requires PGA_GAIN_CTRL_EN_CH2 = 1).
• If ARE is enabled, PGA_GAIN_SET_CH2 controls the PGA
gain when ARE is disengaged.
Valid from 4'd0 (0dB) to 4'd10 (30dB), 3dB steps. Default is 0dB.
[3:0]
PGA_GAIN_SET_CH1
• If ARE is disabled, PGA_GAIN_SET_CH1 sets the amount of
PGA gain (requires PGA_GAIN_CTRL_EN_CH1 = 1).
• If ARE is enabled, PGA_GAIN_SET_CH1 controls the PGA
gain when ARE is disengaged.
Valid from 4'd0 (0dB) to 4'd10 (30dB), 3dB steps. Default is 0dB.
Register 71-69: RESERVED
Register 72: PGA SETTINGS
Bits
[7:6]
[5]
[4]
[3:0]
Default
2'd0
1'b0
1'b0
4'd0
Bits
Mnemonic
Description
[7:6]
RESERVED
NA
[5]
PGA_RIN_CH2
CH2 PGA input impedance.
• 1'b0: 2.5kΩ (default)
• 1'b1: 10kΩ
[4]
PGA_RIN_CH1
CH1 PGA input impedance.
• 1'b0: 2.5kΩ (default)
• 1'b1: 10kΩ
[3:0]
RESERVED
NA



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