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ES9826 датащи(PDF) 62 Page - ESS Technology,Inc

номер детали ES9826
подробное описание детали  32-bit High performance 2 Channel ADC w/PGA
PDF  88 Pages
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производитель  ESS [ESS Technology,Inc]
домашняя страница  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9826 датащи(HTML) 62 Page - ESS Technology,Inc

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ES9826 Datasheet
VERSION 0.1.2
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
62
Register 38: PEAK DETECTOR CONFIG
Bits
[7]
[6:2]
[1]
[0]
Default
1'b0
5'd10
1'b0
1'b0
Bits
Mnemonic
Description
[7]
LOCK_PEAK_VALUE
Locks the current peak detector values, for reading back.
Values can be read from Reg237-240.
• 1'b0: Peak detector value can update (default)
• 1'b1: Peak detector value locked
[6:2]
PEAK_DECAY_RATE
Sets the speed at which the peak detector value will decay
when greater than the input signal.
• 5'd0: Instant decay
• 5'd1: Fastest decay
• 5'd10: Default value
• 5'd22: Slowest decay
• Others: Reserved
[1]
EN_PEAK_DETECT_CH2
Enables the ADC CH2 peak detector.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[0]
EN_PEAK_DETECT_CH1
Enables the ADC CH1 peak detector.
• 1'b0: Disabled (default)
• 1'b1: Enabled
Register 39: CH1 PEAK THRESHOLD
Bits
[7:0]
Default
8'hFF
Bits
Mnemonic
Description
[7:0]
PEAK_THRESH_CH1
Threshold value to trigger the PEAK_FLAG in the CH1 peak
detector.
Triggers if the input signal > PEAK_THRESH_CH1.
Shift left 1 bit corresponds to -6dB.
• 8'h01: -48dB
• 8'hFF: 0dB (default)



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