ES9826 datasheet(47/88 Pages) ESS

47 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

Some reserved registers values might be asserted in default mode. This is normal and does not need to be changed.

System Registers

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Default

1'b0

1'b1

1'b0

1'b1

1'b0

Bits

Mnemonic

Description

[7]

SOFT_RESET

Performs soft reset to digital core and clocked registers (0-80).

[6]

AUTO_FS_BLOCK_64FS

Disable AUTO_FS_DETECT from entering 64FS mode.

• 1'b0: 64FS mode allowed (default)

• 1'b1: 64FS mode blocked

[5]

AUTO_FS_DETECT

Automatic sample rate (FS) detection.

• 1'b0: Disabled, use the values of SELECT_ADC_NUM &

SELECT_ADC_HALF to determine FS

• 1'b1: Automatically tune the MCLK/CLK_ADC ratio

according to detected FS (default)

[4]

ENABLE_64FS_MODE

Enables 64FS mode for 768k sample rate.

• 1'b0: Disabled (default)

• 1'b1: Enabled

[3]

ENABLE_SPDIF_ENCODE

Enables S/PDIF encoding clock.

• 1'b0: S/PDIF clock disabled (default)

• 1'b1: S/PDIF clock enabled

[2]

ENABLE_TDM_ENCODE

Enables I2S/TDM encoding clock.

• 1'b0: I2S/TDM clock disabled

• 1'b1: I2S/TDM clock enabled (default)

[1]

ENABLE_ADC

Enables ADC decimation path clock.

• 1'b0: Clock disabled (default)

• 1'b1: Clock enabled

[0]

RESERVED

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