CS5535 datasheet(164/555 Pages) NSC

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PMC Functional Description (Continued)

d) If SLP_CLK_EN# is not enabled, and if at least one of

the following PM_OUT_SLPCTL, SLEEP_X, or SLEEP_Y

registers is enabled, then Sleep wakeup is possible only

after the longest delay of the three. The delays could be

zero.

SLP_CLK_EN#

not

enabled,

and

the

PM_OUT_SLPCTL, SLEEP_X, or SLEEP_Y registers are

not enabled, then Sleep wakeup is possible immediately.

f) If SLP_CLK_EN# is enabled and the delay associated

with the PM_OUT_SLPCTL register is longer than or equal

to the delay associated with SLP_CLK_EN#, then the

PCI/IDE outputs will not be disabled.

If enabled, the de-assertion of WORKING is assumed to

remove Working power and all clock sources except 32

kHz; that is, the Standby state is entered. In this state, the

PMC, disables its interface to all circuits connected to

Working power and asserts RESET_OUT# before de-

assertion of WORKING. RESET_OUT# remains asserted

throughout Standby.

WORK_AUX is an auxiliary control for the Standby state

with no specific use. It can be de-asserted any time before

or after WORKING.

WORKING and WORK_AUX are independent controls, but

the use of either implies that Standby state is to be entered.

In both cases, the PMC disables all circuits connected to

Working power and asserts reset. However, since they are

independent, one may be left on while the other is de-

asserted.

4.17.3.4 Wakeup Events

If the system has been put to Sleep, only preprogrammed

wakeup events can get the system running again. The

PMC contains the controls that allow the system to respond

to the selected wakeup events.

On wakeup from Sleep (not Standby, but Sleep Wakeup)

(see Figure 4-53 on page 161), the PMC immediately de-

asserts SLP_CLK_EN# to turn system clocks back on. It

also re-enables PCI/IDE outputs to allow output drivers to

return to their operational levels. Next it de-asserts

SLEEP_X and SLEEP_Y based on programmable delays.

Alternate SLEEP_X and SLEEP_Y interactions are shown

as dotted lines. Lastly, the PMC, re-enables PCI/IDE inputs

after a programmable delay and de-asserts Sleep Request.

The GLCP starts any on-chip PLLs and waits for them to

become stable. Then the GLCP de-asserts SUSP# to the

processor. When the processor de-asserts SUSPA#, the

GLCP de-asserts Sleep Acknowledge. The PMC allows the

wakeup event to assert a System Control Interrupt (SCI).

After a wakeup event:

a) PCI/IDE outputs are re-enabled after SLP_CLK_EN# is

de-asserted.

b) PCI/IDE inputs are re-enabled at Sleep wakeup or after

a programmable delay. Generally, PCI/IDE inputs are nor-

mally used with a delay and that delay is longer than any

de-assertion delay associated with SLEEP_X and/or

SLEEP_Y. Re-enabling PCI/IDE inputs is generally not

useful at the beginning of a wakeup sequence.

c) Sleep Request is de-asserted at Sleep wakeup or after a

programmable delay. Sleep Request is kept de-asserted

until the PCI/IDE inputs are re-enabled. Generally, the

enable and delay values in PM_SED (PMS I/O Offset 14h)

and PM_IN_SLPCTL (PMS I/O Offset 20h) should always

be the same.

d) If used, SLEEP_X/SLEEP_Y delay should be set to

occur

between

the

delays

programmed

PM_OUT_SLPCTL

(PMS

I/O

Offset

0Ch)

and

PM_IN_SLPCTL (PMS I/O Offset 20h). If the delays for

SLEEP_X/SLEEP_Y are longer than the PM_IN_SLPCTL

delay, then SLEEP_X/SLEEP_Y de-assert at the same

time as the PCI/IDE inputs are re-enabled.

On wakeup from Standby (not Sleep, but Standby Wakeup)

the PMC asserts WORKING and performs a system reset.

RESET_OUT# is de-asserted after a programmable delay

and the normal software start-up sequence begins. How-

ever, early in the sequence, the software checks the PMC

state to determine if waking from Standby (PMS I/O Offset

54h[0]). If yes, then the system state is potentially restored

from non-volatile storage.

If enabled, WORK_AUX may be asserted before or after

RESET_OUT# is de-asserted.

4.17.3.5 Fail-Safe Power Off

The PMC provides the support logic to implement an ACPI

compliant fail-safe power off button. This logic uncondition-

ally de-asserts the WORKING and WORK_AUX signals if

the On/Off button is held down for a programmable delay.

For ACPI compliance, this delay should be set to four sec-

onds.

4.17.3.6 Wake Events Status and SCI

When enabled, a wake event from the general wake events

isters" on page 462) set its status bit and the "WAK_STS"

bit and causes a system control interrupt (SCI). The Sleep

button, RTC alarm, and power button when asserted,

always set their status bit. They set the "WAK_STS" bit and

generate an SCI only when their enable bit is set. When

overflowed, the PM timer sets its status bit. This overflow

condition does not cause a wakeup event but if enabled, it

generates an SCI. The event’s status is cleared by writing a

one to it.

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