CS5535 datasheet(157/555 Pages) NSC

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MFGPT Functional Description (Continued)

4.16.4.1 Clock Selection and Counter Increment

The MFGPT can use either the 32 kHz clock or 14.318

MHz clock as the clock source (MFGPT6 and MFGPT7 in

Standby power domain are limited to the 32 kHz clock).

When the Counter Enable bit is high, the MFGPT is acti-

vated and capable of counting. An actual increment is per-

formed when the selected prescaler divide-by signals the

increment; this is done through the Scale Factor selecting

one of 16 signals. Table 4-32 shows how the Scale Factor

effectively divides down the incoming clock.

4.16.4.2 Compare 1 and Compare 2 Outputs

When the Up Counter reaches the Compare 1 Value, the

Compare 1 Output is asserted. When the Compare 2 Value

is reached, the Compare 2 Output is asserted, and the Up

Counter then synchronously clears and restarts. The

MFGPT outputs coming from Compare 1 and Compare 2

are all glitch-free outputs.

The compare outputs and events may change in the middle

of a prescaler period if new values are written to the Up

Counter, Compare 1 Value, or Compare 2 Value registers.

These compare outputs can be used to trigger their

respective events and drive GPIO outputs. The events are

used to trigger interrupts, NMI, and reset.

4.16.4.3 GPIO Input

The Up Counter could also be software selected to have a

GPIO input positive edge as another source for the counter

to clear and restart. The GPIO input signal is asynchronous

to the timer and the timer uses a flip-flop to capture the

GPIO rising edge. It takes up to one prescaler clock period

plus two MFGPT clock periods from the GPIO rising edge

for the clear to take effect. Once the counter is cleared, this

edge detect circuit can then accept a new GPIO edge.

Each individual pulse can be as short as a few nanosec-

onds wide for the rising edge to be captured. If this feature

is not selected or the counter is disabled, the clear counter

output and the edge detector are kept de-asserted.

4.16.4.4 Bit Reverse and Pulse Density Modulation

Figure 4-52 shows how the Little Endian/Big Endian Bit

Reverse functions.

Table 4-33 on page 158 shows a 3-bit example of pulse

density modulation; note that the MFGPT has a 16-bit

implementation. If the desired pulse train is of the opposite

polarity, this can be inverted in the GPIO or generated with

a different Compare 1 value.

Figure 4-52. MFGPT Bit Reverse Logic

Table 4-32. MFGPT Prescaler Clock Divider

Scale Factor

Input Clock Divide-By

0000

0001

0010

0011

0100

0101

0110

0111

128

1000

256

1001

512

1010

1024

1011

2048

1100

4096

1101

8192

1110

16384

1111

32768

Input Word from Up Counter

Output Word to Compare Circuit

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