CS5535 datasheet(155/555 Pages) NSC

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MFGPT Functional Description (Continued)

Compare Status/Event Bits

The Setup register also contains two status bits: one from

Compare 1 and one from Compare 2. If Event mode is

selected, then these two status bits represent the events

from the two Compare circuits, and writing a 1 to one of the

bits would clear that particular event. If Event mode is not

selected, then the status bits read back the compare out-

puts, and writing to those bits has no effect. Note that since

this logic is in the Working power domain, MFGPT6 and

MFGPT7 would lose these events when VCORE is powered

off. In order for events to be captured again, the chip has to

have VCORE powered up out of Standby mode and then

come out of reset.

The Compare 1 and Compare 2 outputs may change

simultaneously on the same MFGPT clock edge. However,

when checking the outputs through the two status bits after

this occurred, on rare occasions the read may find only one

of the two outputs changed to the new value. This could

occur when the two outputs change at about the same time

they are synchronized, by separate synchronizers to the

local bus clock domain, and one synchronizer captured the

new value in time while the other one does not. A subse-

quent read can show that both outputs did change states.

4.16.2.3 Register Initialization Sequence for Event

Mode

If the Setup register is written before the other three I/O

registers, and if Event mode is selected for Compare 1

mode or Compare 2 mode, then events will be triggered

immediately. This is because the compare outputs will look

for a Compare register value greater than or equal to the

counter, and the result will be true as those registers are all

0. To avoid triggering these events on Setup register initial-

ization, first initialize the Compare 1 Value and Compare 2

Value registers before initializing the Setup register.

4.16.2.4 Register Data Transfer to/from MFGPT

Only WORD writes and DWORD writes are accepted for

I/O register accesses; BYTE writes to I/O registers are

ignored. The DWORD write would cause the two I/O regis-

ters located within the DWORD boundaries to be written in

parallel. If Up Counter, Compare 1 Value, or Compare 2

Value registers are written while the MFGPT is running, it

could cause the compare outputs to change in the middle

of a prescaler period (i.e., not at a clock cycle where the

prescaler signals a counter increment). For MFGPT0 to

MFGPT5, the clock switch circuitry disables all clocks to

MFGPT until the Setup register has been written. There-

fore, even if the Up Counter, Compare 1 Value, and/or

Compare 2 Value registers are written before the Setup

timer at the same time as the Setup register values.

All reads and writes to MFGPT registers can be done by

software at any time and are completed without requiring

any additional software operation and without affecting the

proper operation of the MFGPT as long as a clock to the

MFGPT has been selected by writing to the Setup register.

On a write, the write transfer on the bus is considered com-

plete when the write to the register in the I/O register sub-

module is complete. This occurs before the register data is

transferred to the timer. However, a subsequent read or

write to the same register will be held up until that first write

transfer to the timer is complete.

The Setup register, except for bits 13 and 14, are handled

in the same way as the Compare 1 Value and Compare 2

Value registers. Bits 13 and 14 write and read were dis-

cussed earlier, where the entire logic is in the Working

power domain.

4.16.2.5 Register Re-initialization

If it is necessary to re-initialize the Up Counter, Compare 1

Value, or Compare 2 Value, the following sequence should

be followed to prevent any spurious reset, interrupt, or out-

put pulses from being created:

Clear Counter Enable bit to 0.

Clear Interrupt Enable, NMI Enable, and Reset Enable

bits in MSRs; disable GPIO inputs and outputs.

Update Up Counter, Compare 1 Value, and Compare

2 Value registers as desired.

When updates are completed, clear any event bits that

are set.

Set up Interrupt Enable, NMI Enable, and Reset

Enable bits in MSRs; enable desired GPIO inputs and

outputs.

Set Counter Enable bit to 1.

4.16.3 Clock Switch

The clock switch output is disabled at reset and selection

can only be done one time after reset, at the first write to

Setup register.

Restriction on Register Read/Write Sequence Due to

Clock Switch

Note that because the timer clock is stopped until the first

write to the Setup register, a write to one of the other three

I/O registers during this time could not complete its transfer

to the timer. As a result, a second access, read or write, to

the same register will cause the bus interface to hang, as

the second access waits for the first access (the initial

write) to complete before completing its own operation. But

since the first access cannot complete without a clock, the

second access is in limbo. This means no more accesses

can occur, so there is no way to write to the Setup register

to enable the timer clock. Care should be taken to see that

this situation does not occur.

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