CS5535 datasheet(370/555 Pages) NSC

370 / 555 page

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370

Revision 0.8

UART/IR Controller Register Descriptions (Continued)

EIR Extended Mode Bit Descriptions

Bit

Name

Description

7:6

RSVD

Reserved. Read as 0.

TXEMP_EV

Transmitter Empty Event. This bit is the same as bit 6 of the LSR (Length Status

4DMA_EV

DMA Event. This bit is set to 1 when a DMA terminal count (TC) is activated. It is

cleared upon read.

MS_EV

Modem Status Event.

• In UART mode:

— This bit is set to 1 when any of the 0 to 3 bits in the MSR is set to 1.

• In any IR mode:

— The function of this bit depends on the setting of IRMSSL of the IRCR2

When IRMSSL is 0, the bit functions as a modem status interrupt event;

when IRMSSL is set to 1, the bit is forced to 0.

LS_EV/TXHLT_EV

Link Status Event

• In UART, Sharp-IR and SIR:

— This bit is set to 1 when a receiver error or break condition is reported. When

FIFOs are enabled, the parity error, frame error and break conditions are

reported only when the associated character reaches the bottom of the

RX_FIFO. An overrun error is reported as soon as it occurs.

Link Status Event or Transmitter Halted Event

• In CEIR:

— Set to 1 when the receiver is overrun or the transmitter underrun.

Note:

A high-speed CPU can service the interrupt generated by the last frame

byte reaching the RX_FIFO bottom before that byte is transferred to mem-

ory by the DMA controller. This can happen when the CPU interrupt

latency is shorter than the RX_FIFO timeout. A DMA request is generated

only when the RX_FIFO level reaches the DMA threshold or when a FIFO

timeout occurs, in order to minimize the performance degradation due to

DMA signal handshake sequences. If the DMA controller must be set up

before receiving each frame, the software in the interrupt routine should

make sure that the last byte of the frame received has been transferred to

memory before reinitializing the DMA controller, otherwise that byte could

appear as the first byte of the next frame received.

TXLDL_EV

Transmitter Low-Data-Level Event. (Default = 1.)

• FIFOs disabled:

— Set to 1 when the transmitter holding register is empty.

• FIFOs enabled:

— Set to 1 when the TX_FIFO level is below the threshold level.

RXHDL_EV

Receiver High-Data-Level Event.

• FIFOs disabled:

— Set to 1 when a character is in the receiver holding register.

• FIFOs enabled:

— Set to 1 when the RX_FIFO is equal to or above threshold or an RX_FIFO

timeout has occurred.

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