CS5535 datasheet(369/555 Pages) NSC

369 / 555 page

Revision 0.8

369

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UART/IR Controller Register Descriptions (Continued)

IER, Non-Extended Mode: UART, SIR or Sharp-IR (EXCR1.EXT_SL = 0)

Upon reset, the IER supports UART, SIR and Sharp-IR in non-extended modes.

5.12.3.3

Event Identification (EIR)/FIFO Control Registers (FCR)

The Event Identification Register (EIR) is a read-only register and shares the same address as the write-only FIFO Control

Event Identification Register (EIR)

The EIR indicates the interrupt source, and operates in two modes, non-extended mode (EXT_SL of the EXCR1 register =

0), and extended mode (EXT_SL of the EXCR1 register = 1) (Bank 2, I/O Offset 02h[0]). In non-extended mode (default),

this register functions the same as in the 16550 mode.

EIR, Extended Mode (EXCR1.EXT_SL = 1)

In extended mode, each of the previously prioritized and encoded interrupt sources is broken down into individual bits.

Each bit in this register acts as an interrupt pending flag, and is set to 1 when the corresponding event has occurred or is

pending, regardless of the IER register bit setting. When this register is read, the DMA event (bit 4) is cleared if an 8237

type DMA is used. All other bits are cleared when the corresponding interrupts are acknowledged, by reading the relevant

IER Non-Extended Mode Register Map

RSVD

MS_IE

LS_IE

TXLDL_IE

RXHDL_IE

IER Non-Extended Mode Bit Descriptions

Bit

Name

Description

7:4

RSVD

Reserved. Write as 0.

3MS_IE

Modem Status Interrupt Enable. Setting this bit to 1 enables the interrupts on modem

status events. (EIR bits [3:0] are 0000.)

2LS_IE

Link Status Interrupt Enable. Setting this bit to 1 enables interrupts on Link Status

events. (EIR bits [3:0] are 0110)

TXLDL_IE

Transmitter Low Data Level Interrupt Enable. Setting this bit to 1 enables interrupts

on transmitter low data level events. (EIR bits [3:0] are 0010.)

RXHDL_IE

Receiver High Data Level Interrupt Enable. Setting this bit to 1 enables interrupts on

receiver high data level, or RX_FIFO timeout events. (EIR bits [3:0] are 0100 or 1100.)

I/O Offset

02h

Type

Reset Value

Extended Mode: 22h

Non-Extended Mode: 01h

EIR Extended Mode Register Map

RSVD

TXEMP_EV

DMA_EV

MS_EV

LS_EV/TXHLT_

TXLDL_EV

RXHDL_EV

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