CS5535 datasheet(368/555 Pages) NSC

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Revision 0.8

UART/IR Controller Register Descriptions (Continued)

5.12.3.2

Interrupt Enable Register (IER)

IER controls the enabling of various interrupts. Some interrupts are common to all operating modes of the functional block,

while others are mode-specific. Bits [7:4] can be set in extended mode only. They are cleared in non-extended mode. When

a bit is set to 1, an interrupt is generated when the corresponding event occurs. In non-extended mode, most events can be

identified by reading the LSR and MSR. The receiver high-data-level event can only be identified by reading the EIR regis-

ter after the corresponding interrupt has been generated. In extended mode, events are identified by event flags in the EIR

The bitmap of the IER varies depending on the operating mode of the functional block. The modes can be divided into the

two groups and is selected via the EXT_SL bit in the EXCR1 register (Bank 2, I/O Offset 02h[0]):

• UART, Sharp-IR, SIR and CEIR in extended mode (EXT_SL = 1)

• UART, Sharp-IR and SIR in non-extended mode (EXT_SL = 0)

IER, Extended Mode: UART, SIR, Sharp-IR and CEIR (EXCR1.EXT_SL = 1)

Notes (Extended Mode Only):

If the interrupt signal drives an edge-sensitive interrupt controller input, it is advisable to disable all interrupts by clear-

ing all the IER bits upon entering the interrupt routine, and re-enable them just before exiting it. This guarantees proper

interrupt triggering in the interrupt controller should one or more interrupt events occur during execution of the interrupt

routine.

If an interrupt source must be disabled, the CPU can do so by clearing the corresponding bit of the IER register. How-

ever, if an interrupt event occurs just before the corresponding enable bit of the IER register is cleared, a spurious inter-

rupt may be generated. To avoid this problem, clearing of any IER bit should be done during execution of the interrupt

service routine. If the interrupt controller is programmed for level-sensitive interrupts, clearing IER bits can be per-

formed outside the interrupt service routine, but with the CPU interrupt disabled.

If the LSR, MSR, or EIR registers are to be polled, the interrupt sources (identified via self-clearing bits) should have

their corresponding IER bits set to 0. This prevents spurious pulses on the interrupt output pin.

I/O Offset

01h

Type

R/W

Reset Value

00h

IER Extended Mode Register Map

RSVD

TXEMP_IE

DMA_IE

MS_IE

LS_IE/

TXHLT_IE

TXLDL_IE

RXHDL_IE

IER Extended Mode Bit Descriptions

Bit

Name

Description

7:6

RSVD

Reserved. Write as 0.

TXEMP_IE

Transmitter Empty Interrupt Enable. Setting this bit to 1 enables transmitter empty

interrupts (in all modes).

4DMA_IE

DMA Interrupt Enable. Setting this bit to 1 enables the interrupt on terminal count

when the DMA is enabled.

3MS_IE

Modem Status Interrupt Enable. Setting this bit to 1 enables the interrupts on modem

status events.

LS_IE/TXHLT_IE

Link Status Interrupt Enable/Transmitter Halted Interrupt Enable. Setting this bit

enables link status interrupts and transmitter halted interrupts in CEIR.

TXLDL_IE

Transmitter Low-Data-Level Interrupt Enable. Setting this bit to 1 enables interrupts

when the TX_FIFO is below the threshold level or the transmitter holding register is

empty.

RXHDL_IE

Receiver High-Data-Level Interrupt Enable. Setting this bit to 1 enables interrupts

when the RXD is full, or the RX_FIFO is equal to or above the RX_FIFO threshold level,

or an RX_FIFO timeout occurs.

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