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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5535 датащи(PDF) 241 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 241 Page - National Semiconductor (TI) |
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241 / 555 page  Revision 0.8 241 www.national.com ACC Register Descriptions (Continued) 5.3.2.5 Second Level Audio IRQ Status Register (ACC_IRQ_STATUS) ACC I/O Offset 12h Type RO Reset Value 00000000h ACC_IRQ_STATUS Register Map 15 14 13 12 11 10 987 6543 210 RSVD ACC_IRQ_STATUS Bit Descriptions Bit Name Description 15:10 RSVD Reserved. Reads return 0. 9 BM7_IRQ_STS Audio Bus Master 7 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 7. Reading the Bus Master 7 IRQ Status Register clears this bit. 8 BM6_IRQ_STS Audio Bus Master 6 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 6. Reading the Bus Master 6 IRQ Status Register clears this bit. 7 BM5_IRQ_STS Audio Bus Master 5 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 5. Reading the Bus Master 5 IRQ Status Register clears this bit. 6 BM4_IRQ_STS Audio Bus Master 4 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 4. Reading the Bus Master 4 IRQ Status Register clears this bit. 5 BM3_IRQ_STS Audio Bus Master 3 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 3. Reading the Bus Master 3 IRQ Status Register clears this bit. 4 BM2_IRQ_STS Audio Bus Master 2 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 2. Reading the Bus Master 2 IRQ Status Register clears this bit. 3 BM1_IRQ_STS Audio Bus Master 1 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 1. Reading the Bus Master 1 IRQ Status Register clears this bit. 2 BM0_IRQ_STS Audio Bus Master 0 IRQ Status. If this bit is set, it indicates that an IRQ was caused by an event occurring on Audio Bus Master 0. Reading the Bus Master 0 IRQ Status Register clears this bit. 1WU_IRQ_STS Codec GPIO Wakeup IRQ Status. If this bit is set, it indicates that an IRQ was caused by a GPIO Wakeup Interrupt event (serial data in going high during power-down). Reading the Codec GPIO Status Register clears this bit. 0IRQ_STS Codec GPIO IRQ Status. If this bit is set, it indicates that an IRQ was caused by a GPIO event in the AC97 Codec (slot 12, bit 0). Reading the Codec GPIO Status Regis- ter clears this bit. |
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