CS5535 datasheet(243/555 Pages) NSC

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ACC Register Descriptions (Continued)

5.3.2.7

Audio Bus Master 0-7 Command Registers (ACC_BM[x]_CMD)

Bus Master 0 Command (ACC_BM0_CMD)

Bus Master 1 Command (ACC_BM1_CMD)

Bus Master 2 Command (ACC_BM2_CMD)

Bus Master 3 Command (ACC_BM3_CMD)

Bus Master 4 Command (ACC_BM4_CMD)

Bus Master 5 Command (ACC_BM5_CMD)

Bus Master 6 Command (ACC_BM6_CMD)

Bus Master 7 Command (ACC_BM7_CMD)

ACC I/O Offset

20h

Type

R/W

Reset Value

00h

ACC I/O Offset

28h

Type

R/W

Reset Value

08h

ACC I/O Offset

30h

Type

R/W

Reset Value

00h

ACC I/O Offset

38h

Type

R/W

Reset Value

08h

ACC I/O Offset

40h

Type

R/W

Reset Value

00h

ACC I/O Offset

48h

Type

R/W

Reset Value

08h

ACC I/O Offset

50h

Type

R/W

Reset Value

00h

ACC I/O Offset

58h

Type

R/W

Reset Value

00h

ACC_BM[x]_CMD Register Map

RSVD

BYTE_ORD

BM_CTL

ACC_BM[x]_CMD Bit Descriptions

Bit

Name

Description

7:4

RSVD

Reserved. Reads return 0

3RW (RO)

Read or Write (Read Only). Indicates the transfer direction of the audio bus master.

This bit always reads 0 for BM [0,2,4,6,7].

This bit always reads 1 for BM[1,3,5].

0: Memory to codec.

1: Codec to memory.

BYTE_ORD

Byte-Order. Sets the byte order for 16-bit samples that this bus master uses.

0: Little Endian (Intel) byte-order (LSBs at lower address).

1: Big Endian (Motorola) byte-order (MSBs at lower address).

1:0

BM_CTL

Bus Master Pause/Enable Control. Enables, disables, or pauses the bus master.

00: Disable bus master.

01: Enable bus master.

10: Reserved.

11: Pause bus master (if currently enabled) or do nothing (if currently disabled).

When the bus master is enabled by writing 01, the bus master starts up by using the

address in its associated PRD Table Address Register. Writing 00 while the bus master

is enabled causes the bus master to stop immediately. Upon resuming the bus master

uses the address in its PRD Table Address Register. The PRD Table Address Register

must be re-initialized by software before enabling the bus master, or there is a risk that

the bus master may overstep the bounds of the PRD Table.

Note:

When the bus master reaches a PRD with the EOT bit set, these bits are set to

00.

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