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CS5535 датащи(PDF) 238 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 238 Page - National Semiconductor (TI) |
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238 / 555 page ![]() www.national.com 238 Revision 0.8 ACC Register Descriptions (Continued) 5.3.2.3 Codec Status Register (ACC_CODEC_STATUS) 19:0 PIN_DATA Codec GPIO Pin Data. This is the GPIO pin data that is sent to the codec in slot 12 of the serial output stream. Note: All 20 bits of the output slot 12 are controllable through this register, even though some are reserved per the AC97 spec and should be set to zero. ACC I/O Offset 08h Type R/W Reset Value 00000000h ACC_CODEC_STATUS Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 STS_ADD STS_DATA ACC_CODEC_STATUS Bit Descriptions Bit Name Description 31:24 STS_ADD Codec Status Address (Read Only). Address of the register for which status is being returned. This address comes from slot 1 bits [19:12] of the serial input stream. Note: Bit 19 of slot 1 is reserved, but still observable by software. 23 PRM_RDY_STS Primary Codec Ready (Read Only). Indicates the ready status of the primary codec (slot 0, bit 15). Software should not access the codec or enable any bus masters until this bit is set. This bit is cleared when the AC Link Shutdown bit is set in the Codec Control register (ACC I/O Offset 0Ch[18]). 22 SEC_RDY_STS Secondary Codec Ready (Read Only). Indicates the ready status of the secondary codec (slot 0, bit 15). Software should not access the codec or enable any bus masters until this bit is set. This bit is cleared when the AC Link Shutdown bit is set in the Codec Control register (ACC I/O Offset 0Ch[18]). 21 SDATAIN2_EN Enable Second Serial Data Input (AC_S_IN2) . 0: Disable. 1: Enable. For the second serial input to function, this bit must be set. This is functionally ANDed with the AC_S_IN2 port of the ACC. Often, it may be necessary to configure a corre- sponding I/O pin as an input on the chip containing the ACC. 20 BM5_SEL Audio Bus Master 5 AC97 Slot Select. Selects the serial input slot for Audio Bus Mas- ter 5 to receive data. 0: Slot 6. 1: Slot 11. 19 BM4_SEL Audio Bus Master 4 AC97 Slot Select. Selects slot for Audio Bus Master 4 to transmit data. 0: Slot 6. 1: Slot 11. 18 RSVD Reserved. Reads return 0 ACC_GPIO_CNTL Bit Descriptions Bit Name Description |
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