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CS5535 датащи(PDF) 219 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 219 Page - National Semiconductor (TI) |
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219 / 555 page ![]() Revision 0.8 219 www.national.com GLPCI_SB Register Descriptions (Continued) 5.2.1.6 GeodeLink Device Diagnostic MSR (GLPCI_GLD_MSR_DIAG) This register is reserved for internal use by National and should not be written to. 5.2.2 GLPCI_SB Specific MSRs 5.2.2.1 Global Control (GLPCI_CTRL) 1:0 PMODE0 Power Mode 0. Power mode for GLIU clock domain. 00: Disable clock gating. Clocks are always on. 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10: Reserved. 11: Reserved. MSR Address 51000005h Type R/W Reset Value 00000000_00000000h MSR Address 51000010h Type R/W Reset Value 44000030_00000003h GLPCI_CTRL Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 FTH RTH RSVD RTL RSVD ILTO LAT 000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RSVD SUS FPIDE RSVD CISM GLPCI_CTRL Bit Descriptions Bit Name IB/OB Description 63:60 FTH IB In-Bound Flush Threshold. Controls the timing for requesting new read data while concurrently flushing previously prefetched, stale read data. While flushing stale data, if the number of prefetched 64-bit WORDs reaches this level, then a new read request is made. 59:56 RTH IB In-Bound Read Threshold. Controls the timing for prefetching read data. If the number of prefetched 32-bit WORDs is decremented and reaches this threshold, a subsequent GLIU request is generated to fetch the next cache-line of read data. 55:52 RSVD (RO) --- Reserved (Read Only). Returns 0. 51:49 RTL OB Retry Transaction Limit. Limits the number of out-bound retries. If a target signals retry indefinitely the PCI interface may be configured to abort the failing out-bound request. 000: No limit. 100: 64 retries. 001: 8 retries. 101: 128 retries. 010: 16 retries. 110: 256 retries. 011: 32 retries. 111: 512 retries. GLPCI_GLD_MSR_PM Bit Descriptions (Continued) Bit Name Description |
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