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CS5535 датащи(PDF) 217 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 217 Page - National Semiconductor (TI) |
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217 / 555 page ![]() Revision 0.8 217 www.national.com GLPCI_SB Register Descriptions (Continued) GLPCI_GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 RSVD RSVD GLPCI_GLD_MSR_ERROR Bit Descriptions Bit Name Description 63:23 RSVD (RO) Reserved (Read Only). Returns 0. 22 TAS_ERR_ FLAG Target Abort Signaled Error Flag. If high, records that an ERR was generated due to signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect. TAS_ERR_EN (bit 6) must be set to enable this event and set flag. 21 PARE_ERR_ FLAG Parity Error Error Flag. If high, records that an ERR was generated due to the detection of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PARE_ERR_EN (bit 5) must be set to enable this event and set flag. 20 SYSE_ERR_ FLAG System Error Error Flag. If high, records that an ERR was generated due to the detec- tion of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ERR_EN (bit 4) must be set to enable this event and set flag. 19 EXCEP_ERR_ FLAG Exception Bit Error Flag. If high, records that the EXCP bit in the received GLIU read or write response packet is set. Write 1 to clear. EXCEP_ERR_EN (bit 3) must be set to enable this event and set flag. 18 RSVD (RO) Reserved (Read Only). Returns 0. 17 TAR_ERR_ FLAG Target Abort Received Error Flag. If high, records that an ERR was generated due to the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect. TAR_ERR_EN (bit 1) must be set to enable this event and set flag. 16 MAR_ERR_ FLAG Master Abort Received Error Flag. If high, records that an ERR was generated due to the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect. MAR_ERR_EN (bit 0) must be set to enable this event and set flag. 15:7 RSVD (RO) Reserved (Read Only). Returns 0. 6 TAS_ERR_EN Target Abort Signaled Error Enable. Write 1 to enable TAS_ERR_FLAG (bit 22) and to allow the event to generate an ERR. 5 PARE_ERR_EN Parity Error Error Enable. Write 1 to enable PAR_ERR_FLAG (bit 21) and to allow the event to generate an ERR. 4 SYSE_ERR_EN System Error Error Enable. Write 1 to enable SYSE_ERR_FLAG (bit 20) and to allow the event to generate an ERR. 3 EXCEP_ERR_ EN Exception Bit Error Enable. Write 1 to enable EXCEP_ERR_FLAG (bit 19) and to allow the event to generate an ERR. 2 RSVD (RO) Reserved (Read Only). Returns 0. 1 TAR_ERR_EN Target Abort Received Error Enable. Write 1 to enable TAR_ERR_FLAG (bit 17) and to allow the event to generate an ERR. 0 MAR_ERR_EN Master Abort Received Enable. Write 1 to enable MAR_ERR_FLAG (bit 16) and to allow the event to generate an ERR. |
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