CS5535 datasheet(179/555 Pages) NSC

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TAP Controller Functional Description (Continued)

Table 4-38. TAP Controller Instructions

Instruction

Length

IR Name

Description

000000h and

FFFFE8h

240

EXTEST

Boundary Scan Ring. IEEE 1149.1 specification compliant.

(Mapped twice in IR address space.)

01FFFAh through

1DFFFAh

Variable

TAPSCAN[0:28]

TAP Scan Chain 0 through Chain 28. These are parts of the

internal scan chain subdivided according to a common CCU

clock.

01FFFFh through

1DFFFFh

TAPFUNC[0:28]

TAP Function Chain 0 through Chain 28. One capture cycle

applied to the individual CCU scan chain clocked by the func-

tional clock.

81FFFAh

GL_ADDR

GeodeLink Address. Access GeodeLink request packet and

data packet control bits.

83FFFAh

GL_DATA

GeodeLink Data. Access GeodeLink data.

85FFFAh

PADACC

Pad Access. Padtestmode for access to analog and memory

BIST signals.

87FFFAh

PROGMISR

Program instruction. This instruction provides direct access to

an MSR used for the ROM memory BIST test. Not supported.

8BFFFAh

GL_ADDR_ACT

GeodeLink Address Action. Same data register as GL_ADDR,

but no GeodeLink transactions are triggered by the access -

only by GLCP debug action.

8DFFFAh

TST_IDDQ

Test IDDQ. Put chip in a mode for running IDDQ tests.

8FFFFAh

REVID

Revision ID. The TAP instruction used to access the current

revision code (8 bits) for the chip.

FFFFDFh

TRISTATE

TRI-STATE. Put chip into TRI-STATE and comparison mode.

FFFFFDh

BISTDR

Parallel RAM BIST. Internal data register (for chip test).

FFFFFEh

IDCODE

ID Code. 0FE1101Fh for CS5535.

MSB

LSB

ID[31:28]

ID27

ID[12:11]

ID[1:0]

Version

Part Number

Manuf. ID

FFFFFFh

BYPASS

Bypass. IEEE 1149.1 specification requires all 1s to be

bypassed.

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