CS5535 datasheet(176/555 Pages) NSC

176 / 555 page

www.national.com

176

Revision 0.8

4.19 GEODELINK CONTROL PROCESSOR

The GeodeLink Control Processor (GLCP) functionality is

illustrated in Figure 4-62 and is summarized as:

• Serial to GeodeLink conversion to facilitate JTAG

accesses to GeodeLink Devices

• Power management support (reset and clock control)

• MSRs

Together with a JTAG controller, the GLCP provides com-

plete visibility of the register state that the chip is in. All reg-

isters are accessible via the JTAG interface.

How the JTAG controller interfaces with the GLCP is

beyond the scope of this document and is not explained

here.

The GLCP also works with the CCU (Clock Control Unit)

blocks of other GeodeLink Devices to provide clock control

via its relevant MSRs. The GLCP supplies the clock enable

signals to all the CCUs, which allows clocks to be shut off if

the power management logic generates a Sleep request or

if a debug event triggers a clock disable situation.

Figure 4-62. GLCP Block Diagram

4.19.1 GeodeLink Power Management Support

The main power management functions are performed by

the Power Management Logic, with the GLCP playing a

supporting role. (See Section 4.17 "Power Management

Control" on page 159 for a complete understanding of

power management.)

4.19.1.1 Soft Reset

This is one of the active high soft reset sources going to the

Power

Management

Logic.

resides

the

GLCP_SYS_RST register. When active, all circuitry in the

CS5535 chip is reset (including the GLCP_SYS_RST reg-

ister itself).

4.19.1.2 Clock Control

The GLCP provides a mechanism to shut off clocks. The

busy signal from a module can control the clock gating in

its CCU, however, clocks can also be enabled or disabled

by the functional clock enable signals coming from the

GLCP. These enable signals are asynchronous to the mod-

ules and need to be synchronized in the CCU blocks before

being used to enable or disable the functional clocks.

The clocks can be disabled in one or a combination of the

three ways below. All the MSRs mentioned can be found in

Section 5.18 "Power Management Controller Register

Descriptions" on page 477 and Section 5.20 "GeodeLink

Control Processor Register Descriptions" on page 513.

The power management circuitry disables the clocks

when going into Sleep. The Sleep sequence is started

by the assertion of Sleep Request from the Power

Management Logic. The GLCP asserts Sleep Request

and waits for the assertion of Sleep Acknowledge,

which indicates that the clocks should be disabled.

There are two ways to do this:

– If Sleep Acknowledge is asserted and the clock

disable delay period has expired, disable the

clocks specified in GLCP_PMCLKDISABLE (MSR

51700009h). Each bit in GLCP_PMCLKDISABLE

corresponds to a CCU, and when set, indicates

that the clock going to that CCU should be

disabled during a Sleep sequence. The clock

disable delay period is specified by the

CLK_DELAY bits in GLCP_CLK_DIS_DELAY

(MSR 51700008h), and is enabled by the

CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh). It is clocked by the PCI functional

clock.

Serial to GL

Conversion

MSR Registers

Power

Management

Support

PCI Interface

Req

Data Data

TAP Controller

PCI Clock

GeodeLink Interface

Out

CS5535 датащи(PDF) 176 Page - National Semiconductor (TI)

CS5535 датащи(HTML) 176 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL