NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

tSP

tBUF

tHD;STA

P

P

S

tLOW

tr

tHD;DAT

tf

tHIGH

tSU;DAT

tSU;STA

Sr

tHD;STA

tSU;STO

SDA

SCL

002aaa986

0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

Figure 18. Definition of timing

SDA

SCL

002aad062

trst

50 %

30 %

50 %

50 %

50 %

trec(rst)

tw(rst)

RESET

P0 to P7

output off

START

trst

ACK or read cycle

Figure 19. Reset timing

14 Test information

PULSE

GENERATOR

VO

CL

50 pF

RL

500 Ω

002aad582

RT

VI

VDD

DUT

2VDD

open

VSS

500 Ω(1)

RL = load resistance.

CL = load capacitance includes jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generators.

1. For SDA, no 500 Ω pull-down.

Figure 20. Test circuitry for switching times

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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