NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

VDD = 1.1 V to 3.6 V; VDD(IO) = 1.1 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.

Standard-

mode I2C-bus

Fast-mode I2C-bus

Symbol Parameter

Conditions

Min

Max

Min

Max

Unit

tBUF

bus free time between a STOP and

START condition

4.7

-

1.3

-

μs

tHD;STA

hold time (repeated) START condition

4.0

-

0.6

-

μs

tSU;STA

set-up time for a repeated START

condition

4.7

-

0.6

-

μs

tSU;STO

set-up time for STOP condition

4.0

-

0.6

-

μs

tVD;ACK

data valid acknowledge time

[1]

0.3

3.45

0.1

0.9

μs

tHD;DAT

data hold time

0

-

0

-

ns

tVD;DAT

data valid time

[2]

300

-

50

-

ns

tSU;DAT

data set-up time

250

-

100

-

ns

tLOW

LOW period of the SCL clock

4.7

-

1.3

-

μs

tHIGH

HIGH period of the SCL clock

4.0

-

0.6

-

μs

tf

fall time of both SDA and SCL signals

-

300

20 + 0.1Cb[3]

300

ns

tr

rise time of both SDA and SCL signals

-

1000

20 + 0.1Cb[3]

300

ns

tSP

pulse width of spikes that must be

suppressed by the input filter

-

50

-

50

ns

Port timing

tv(Q)

data output valid time

-

200

-

200

ns

tsu(D)

data input set-up time

150

-

150

-

ns

th(D)

data input hold time

1

-

1

-

μs

Interrupt timing

tv(INT)

valid time on pin INT

-

4

-

4

μs

trst(INT)

reset time on pin INT

-

4

-

4

μs

Reset

tw(rst)

reset pulse width

6

-

6

-

ns

trec(rst)

reset recovery time

0

-

0

-

ns

trst(SDA)

SDA reset time

Figure 19

-

450

-

450

ns

trst(GPIO)

GPIO reset time

Figure 19

-

450

-

450

ns

Table 15. Dynamic characteristics...continued

[1]

tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2]

tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3]

Cb = total capacitance of one bus line in pF.

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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