AD9942BBCZ datasheet(28/36 Pages) AD

28 / 36 page

AD9942

Rev. A | Page 28 of 36

CHANNEL A AND CHANNEL B

VARIABLE GAIN AMPLIFIER

The VGA stage provides a gain range of 0 dB to 18 dB, pro-

grammable with 9-bit resolution through the serial digital

interface. A minimum gain of 6 dB is needed to match a 1 V

input signal with the ADC full-scale range of 2 V.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain can be calculated for any gain register value by

using the equation

Gain (dB) = (0.035 × VGAGAIN Code)

where the code range is 0 to 511.

100

150

200

250

300

350

400

450

500

GAIN CODE (Decimal)

Figure 29. VGA Gain Curve

CHANNEL A AND CHANNEL B ADC

The AD9942 uses a high performance ADC architecture, opti-

mized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.5 LSB. The ADC

uses a 2 V input range. See Figure 8 and Figure 9 for typical

linearity and noise performance plots for the AD9942.

CHANNEL A AND CHANNEL B CLPOB

The CLPOB loop is used to remove residual offsets in the signal

chain and to track low frequency variations in the CCD black

level. During the optical black (OB), or shielded, pixel interval

on each line, the ADC output is compared with a fixed black

level reference, selected by the user in the CLAMP LEVEL

LSB in 256 steps. The resulting error signal is filtered to reduce

noise, and the correction value is applied to the ADC input

through a digital-to-analog converter. Typically, the CLPOB

loop is turned on once per horizontal line, but this loop can be

updated more slowly to suit a particular application. If external

digital clamping is used during postprocessing, the AD9942

CLPOB can be disabled using Bit D2 in the OPRMODE register.

The CLAMP LEVEL register can be used to provide program-

mable offset adjustment even when the loop is disabled.

The CLPOB pulse should be placed during the CCD’s OB pixel

region. It is recommended that the CLPOB pulse duration be at

least 20 pixels wide to minimize clamp noise. Shorter pulse widths

can be used, but clamp noise might increase and the ability to

track low frequency variations in the black level is reduced. See

the Channel A and Channel B Horizontal Clamping and

Blanking section and the Applications Information section for

timing examples.

CHANNEL A AND CHANNEL B

DIGITAL DATA OUTPUTS

The AD9942 digital output data is latched using the

DOUTPHASE register value, as shown in Figure 28. (Output

data timing is shown in Figure 19 and Figure 20.) It is also possible

to leave the output latches transparent, so that the data outputs

are valid immediately from the ADC. Programming the AFE

Control Register Bit D4 to 1 sets the output latches transparent.

The data outputs can also be disabled (three-stated) by setting

the AFE Control Register Bit D3 to 1.

The data output coding is typically straight binary, but the

coding can be changed to gray coding by setting the AFE

Control Register Bit D5 to 1.

AD9942BBCZ датащи(PDF) 28 Page - Analog Devices

AD9942BBCZ датащи(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL