AD9942BBCZ datasheet(26/36 Pages) AD

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AD9942

Rev. A | Page 26 of 36

CHANNEL A AND CHANNEL B POWER-UP PROCEDURE

When the AD9942 is powered up, the following sequence is

recommended for Channel A and Channel B (see Figure 27 for

each step).

Turn on the power supplies for the AD9942.

Apply the master clock input, CLI_X, VD_X, and HD_X.

Although the AD9942 contains an on-chip power-on reset,

a software reset of the internal registers is recommended.

Write a 1 to the SW_RST register (Address 0x10), which

resets all the internal registers to their default values. This

bit is self-clearing and is automatically reset to 0.

Reset the Precision Timing core by writing a 0 to the

TGCORE_RSTB register (Address 0x12), then write a l to

the TGCORE_RSTB register. This starts the internal

timing core operation.

Write a 1 to the PREVENTUPDATE register (Address 0x14).

This prevents an update of the serial register data.

Write to the desired registers to configure high speed

timing and horizontal timing.

Write a 3 to the [7:6] TESTMODE register (Address 0x00).

See Table 15.

Write a 1 to the OUT_CONTROL register (Address 0x11).

This allows the outputs to become active after the next

VD_X/HD_X rising edge.

Write a 0 to the PREVENTUPDATE register (Address 0x14).

This allows the serial information to be updated at the

next VD_X/HD_X falling edge. The next VD_X/HD_X

falling edge allows register updates, including updates of

OUT_CONTROL, to occur which enables all clock outputs.

VDD

(INPUT)

SERIAL

WRITES

VD_X

(OUTPUT)

ODD FIELD

EVEN FIELD

...

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS

UPDATED AT VD/HD EDGE

H1X/H3X, RG_X

H2X/H4X

tPWR

CLI_X

(INPUT)

HD_X

(OUTPUT)

...

Figure 27. Recommended Power-Up Sequence

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