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AD9942BBCZ датащи(PDF) 18 Page - Analog Devices |
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AD9942BBCZ датащи(HTML) 18 Page - Analog Devices |
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18 / 36 page ![]() AD9942 Rev. A | Page 18 of 36 Table 14. CHN_A and CHN_B H1 to H4, RG, SHP, SHD Register Map Address Data Bit Content Default (Hex) Name Description 60 [12:0] 01001 H1CONTROL H1 signal control. Polarity [0] (0 = inversion; 1 = no inversion). H1 positive edge location [6:1]. H1 negative edge location [12:7]. 61 [12:0] 00801 RGCONTROL RG signal control. Polarity [0] (0 = inversion; 1 = no inversion). RG positive-edge location [6:1]. RG negative-edge location [12:7]. 62 [14:0] 0 DRVCONTROL Drive-strength control for H1X [2:0], H2X [5:3], H3X [8:6], H4X [11:9], and RG_X [14:12]. Drive-current values: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA. 63 [11:0] 00024 SAMPCONTROL SHP/SHD sample control. SHP sampling location [5:0]. SHD sampling location [11:6]. 64 [5:0] 0 DOUTPHASE DOUT phase control. Table 15. CHN_A and CHN_B AFE Operation Register Detail Address Data Bit Content Default (Hex) Name Description 00 [1:0] 0 PWRDOWN 0 = normal operation; 1 = reference standby; 2/3 = total power-down. [2] 1 CLPENABLE 0 = disable CLPOB; 1 = enable CLPOB. [3] 0 CLPSPEED 0 = select normal CLPOB settling; 1 = select fast CLPOB settling. [4] 0 FASTUPDATE 0 = ignore VGA update; 1 = very fast clamping when VGA is updated. [5] 0 PBLK_LVL DOUT value during PBLK; 0 = blank to zero; 1 = blank to clamp level. [7:6] 0 TEST MODE Internal test mode. Should always be set = 3. [8] 0 DCBYP 0 = enable dc restore circuit; 1 = bypass dc restore circuit during PBLK. [9] 0 TESTMODE Test operation only. Set = 0. [11:10] 0 TESTMODE Test operation only. Set = 0. Table 16. CHN_A and CHN_B AFE Control Register Detail Address Data Bit Content Default (Hex) Name Description 03 [1:0] 0 TESTMODE Test operation only. Set = 0. [2] 1 TESTMODE Test operation only. Set = 0. [3] 0 DOUTDISABLE 0 = data outputs are driven; 1 = data outputs are three-stated. [4] 0 DOUTLATCH 0 = latch data outputs with DOUT phase; 1 = output latch transparent. [5] 0 GRAYENCODE 0 = binary encode data outputs; 1 = gray encode data outputs. |
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