AD9942BBCZ datasheet(27/36 Pages) AD

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AD9942

Rev. A | Page 27 of 36

CHANNEL A AND CHANNEL B ANALOG FRONT END OPERATION

The AD9942 signal processing chain is shown in Figure 28.

Each processing step is essential for achieving a high quality

image from the raw CCD pixel data.

DC RESTORE

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 μF series coupling

capacitor. This restores the dc level of the CCDIN_X signal to

approximately 1.5 V to be compatible with the 3 V supply

voltage of the AD9942.

CORRELATED DOUBLE SAMPLER

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

shown in Figure 17 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and the CCD signal level, respectively. The placement of

the SHP and SHD sampling edges is determined by the setting

of the SAMPCONTROL register located at Address 0x63.

Placement of these two clock signals is critical for achieving the

best performance from the CCD.

CCDIN_X

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

ADC

DAC

CDS

INTERNAL

VREF

2V FULL SCALE

0dB ~ 18dB

SHP

SHD

VGA1

1.5V

OUTPUT

DATA

LATCH

REFT_X

REFB_X

DOUT

PHASE

PBLK

1.0V

2.0V

DOUT

AD9942

1.0µF 1.0µF

1.0µF

VGA GAIN

REGISTERS

CLAMP LEVEL

CLPOB PBLK

V-H

TIMING

GENERATION

SHP SHD

DOUT

PHASE

PRECISION

TIMING

GENERATION

Figure 28. Channel A and Channel B Analog Front End Functional Block Diagram

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